OLD | NEW |
1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <assert.h> | 5 #include <assert.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdio.h> | 7 #include <stdio.h> |
8 | 8 |
9 #if V8_TARGET_ARCH_X87 | 9 #if V8_TARGET_ARCH_X87 |
10 | 10 |
(...skipping 888 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
899 return 2; | 899 return 2; |
900 } | 900 } |
901 | 901 |
902 | 902 |
903 // Mnemonics for instructions 0xF0 byte. | 903 // Mnemonics for instructions 0xF0 byte. |
904 // Returns NULL if the instruction is not handled here. | 904 // Returns NULL if the instruction is not handled here. |
905 static const char* F0Mnem(byte f0byte) { | 905 static const char* F0Mnem(byte f0byte) { |
906 switch (f0byte) { | 906 switch (f0byte) { |
907 case 0x0B: | 907 case 0x0B: |
908 return "ud2"; | 908 return "ud2"; |
909 case 0x18: return "prefetch"; | 909 case 0x18: |
910 case 0xA2: return "cpuid"; | 910 return "prefetch"; |
911 case 0xBE: return "movsx_b"; | 911 case 0xA2: |
912 case 0xBF: return "movsx_w"; | 912 return "cpuid"; |
913 case 0xB6: return "movzx_b"; | 913 case 0xBE: |
914 case 0xB7: return "movzx_w"; | 914 return "movsx_b"; |
915 case 0xAF: return "imul"; | 915 case 0xBF: |
916 case 0xA5: return "shld"; | 916 return "movsx_w"; |
917 case 0xAD: return "shrd"; | 917 case 0xB6: |
918 case 0xAC: return "shrd"; // 3-operand version. | 918 return "movzx_b"; |
919 case 0xAB: return "bts"; | 919 case 0xB7: |
920 case 0xBD: return "bsr"; | 920 return "movzx_w"; |
| 921 case 0xAF: |
| 922 return "imul"; |
| 923 case 0xA4: |
| 924 return "shld"; |
| 925 case 0xA5: |
| 926 return "shld"; |
| 927 case 0xAD: |
| 928 return "shrd"; |
| 929 case 0xAC: |
| 930 return "shrd"; // 3-operand version. |
| 931 case 0xAB: |
| 932 return "bts"; |
| 933 case 0xBC: |
| 934 return "bsf"; |
| 935 case 0xBD: |
| 936 return "bsr"; |
921 default: return NULL; | 937 default: return NULL; |
922 } | 938 } |
923 } | 939 } |
924 | 940 |
925 | 941 |
926 // Disassembled instruction '*instr' and writes it into 'out_buffer'. | 942 // Disassembled instruction '*instr' and writes it into 'out_buffer'. |
927 int DisassemblerX87::InstructionDecode(v8::internal::Vector<char> out_buffer, | 943 int DisassemblerX87::InstructionDecode(v8::internal::Vector<char> out_buffer, |
928 byte* instr) { | 944 byte* instr) { |
929 tmp_buffer_pos_ = 0; // starting to write as position 0 | 945 tmp_buffer_pos_ = 0; // starting to write as position 0 |
930 byte* data = instr; | 946 byte* data = instr; |
(...skipping 196 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1127 } else if ((f0byte & 0xF0) == 0x80) { | 1143 } else if ((f0byte & 0xF0) == 0x80) { |
1128 data += JumpConditional(data, branch_hint); | 1144 data += JumpConditional(data, branch_hint); |
1129 } else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 || | 1145 } else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 || |
1130 f0byte == 0xB7 || f0byte == 0xAF) { | 1146 f0byte == 0xB7 || f0byte == 0xAF) { |
1131 data += 2; | 1147 data += 2; |
1132 data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data); | 1148 data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data); |
1133 } else if ((f0byte & 0xF0) == 0x90) { | 1149 } else if ((f0byte & 0xF0) == 0x90) { |
1134 data += SetCC(data); | 1150 data += SetCC(data); |
1135 } else if ((f0byte & 0xF0) == 0x40) { | 1151 } else if ((f0byte & 0xF0) == 0x40) { |
1136 data += CMov(data); | 1152 data += CMov(data); |
1137 } else if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) { | 1153 } else if (f0byte == 0xA4) { |
1138 // shrd, shld, bts | |
1139 data += 2; | 1154 data += 2; |
1140 AppendToBuffer("%s ", f0mnem); | 1155 AppendToBuffer("%s ", f0mnem); |
1141 int mod, regop, rm; | 1156 int mod, regop, rm; |
| 1157 get_modrm(*data, &mod, ®op, &rm); |
| 1158 int8_t imm8 = static_cast<int8_t>(data[1]); |
| 1159 data += 2; |
| 1160 AppendToBuffer("%s,%s,%d", NameOfCPURegister(rm), |
| 1161 NameOfCPURegister(regop), static_cast<int>(imm8)); |
| 1162 } else if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) { |
| 1163 // shrd, shld_cl, bts |
| 1164 data += 2; |
| 1165 AppendToBuffer("%s ", f0mnem); |
| 1166 int mod, regop, rm; |
1142 get_modrm(*data, &mod, ®op, &rm); | 1167 get_modrm(*data, &mod, ®op, &rm); |
1143 data += PrintRightOperand(data); | 1168 data += PrintRightOperand(data); |
1144 if (f0byte == 0xAB) { | 1169 if (f0byte == 0xAB) { |
1145 AppendToBuffer(",%s", NameOfCPURegister(regop)); | 1170 AppendToBuffer(",%s", NameOfCPURegister(regop)); |
1146 } else { | 1171 } else { |
1147 AppendToBuffer(",%s,cl", NameOfCPURegister(regop)); | 1172 AppendToBuffer(",%s,cl", NameOfCPURegister(regop)); |
1148 } | 1173 } |
1149 } else if (f0byte == 0xBD) { | 1174 } else if (f0byte == 0xBD) { |
1150 data += 2; | 1175 data += 2; |
1151 int mod, regop, rm; | 1176 int mod, regop, rm; |
(...skipping 643 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1795 fprintf(f, " "); | 1820 fprintf(f, " "); |
1796 } | 1821 } |
1797 fprintf(f, " %s\n", buffer.start()); | 1822 fprintf(f, " %s\n", buffer.start()); |
1798 } | 1823 } |
1799 } | 1824 } |
1800 | 1825 |
1801 | 1826 |
1802 } // namespace disasm | 1827 } // namespace disasm |
1803 | 1828 |
1804 #endif // V8_TARGET_ARCH_X87 | 1829 #endif // V8_TARGET_ARCH_X87 |
OLD | NEW |