Subzero. ARM32. Fix bugs uncovered by scons tests.

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 
@@ skipping 1047 matching lines @@
   %old_ext = zext i8 %old to i32
   ret i32 %old_ext
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_8
 ; CHECK: mov eax,{{.*}}
 ; Need to check that eax isn't used as the address register or the desired.
 ; since it is already used as the *expected* register.
 ; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],{{[^a]}}l
 ; ARM32-LABEL: test_atomic_cmpxchg_8
 ; ARM32: dmb
-; ARM32: ldrexb
-; ARM32: cmp
-; ARM32: {{strb|mov}}
-; ARM32: strexbeq
-; ARM32: cmpeq
+; ARM32: ldrexb [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
+; ARM32: lsl [[VV:r[0-9]+]], [[V]], #24
+; ARM32: cmp [[VV]], {{r[0-9]+}}, lsl #24
+; ARM32: movne [[SUCCESS:r[0-9]+]],
+; ARM32: strexbeq [[SUCCESS]], {{r[0-9]+}}, {{[[]}}[[A]]{{[]]}}
+; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected,
                                             i32 %desired) {
 entry:
   %trunc_exp = trunc i32 %expected to i16
   %trunc_des = trunc i32 %desired to i16
   %ptr = inttoptr i32 %iptr to i16*
   %old = call i16 @llvm.nacl.atomic.cmpxchg.i16(i16* %ptr, i16 %trunc_exp,
                                                i16 %trunc_des, i32 6, i32 6)
   %old_ext = zext i16 %old to i32
   ret i32 %old_ext
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_16
 ; CHECK: mov {{ax|eax}},{{.*}}
 ; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}],{{[^a]}}x
 ; ARM32-LABEL: test_atomic_cmpxchg_16
 ; ARM32: dmb
-; ARM32: ldrexh
-; ARM32: cmp
-; ARM32: {{strh|mov}}
-; ARM32: strexheq
-; ARM32: cmpeq
+; ARM32: ldrexh [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
+; ARM32: lsl [[VV:r[0-9]+]], [[V]], #16
+; ARM32: cmp [[VV]], {{r[0-9]+}}, lsl #16
+; ARM32: movne [[SUCCESS:r[0-9]+]],
+; ARM32: strexheq [[SUCCESS]], {{r[0-9]+}}, {{[[]}}[[A]]{{[]]}}
+; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected,
                                             i32 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
                                                i32 %desired, i32 6, i32 6)
   ret i32 %old
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_32
 ; CHECK: mov eax,{{.*}}
 ; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
 ; ARM32-LABEL: test_atomic_cmpxchg_32
 ; ARM32: dmb
-; ARM32: ldrex
-; ARM32: cmp
-; ARM32: {{str|mov}}
-; ARM32: strexeq
-; ARM32: cmpeq
+; ARM32: ldrex [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
+; ARM32: cmp [[V]], {{r[0-9]+}}
+; ARM32: movne [[SUCCESS:r[0-9]+]],
+; ARM32: strexeq [[SUCCESS]], {{r[0-9]+}}, {{[[]}}[[A]]{{[]]}}
+; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected,
                                             i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
                                                i64 %desired, i32 6, i32 6)
   ret i64 %old
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64
 ; CHECK: push ebx
 ; CHECK-DAG: mov edx
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
 ; edx and eax are already the return registers, so they don't actually
 ; need to be reshuffled via movs. The next test stores the result
 ; somewhere, so in that case they do need to be mov'ed.
 ; ARM32-LABEL: test_atomic_cmpxchg_64
 ; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32: mov
-; ARM32: mov
-; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: cmpeq
+; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
+; ARM32: cmp [[V0]], {{r[0-9]+}}
+; ARM32: cmpeq [[V1]], {{r[0-9]+}}
+; ARM32: movne [[SUCCESS:r[0-9]+]],
+; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
+; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i64 @test_atomic_cmpxchg_64_undef(i32 %iptr, i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 undef,
                                                i64 %desired, i32 6, i32 6)
   ret i64 %old
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64_undef
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
 ; ARM32-LABEL: test_atomic_cmpxchg_64_undef
 ; ARM32: mov r{{[0-9]+}}, #0
 ; ARM32: mov r{{[0-9]+}}, #0
 ; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32: mov
-; ARM32: mov
-; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: cmpeq
+; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
+; ARM32: cmp [[V0]], {{r[0-9]+}}
+; ARM32: cmpeq [[V1]], {{r[0-9]+}}
+; ARM32: movne [[SUCCESS:r[0-9]+]],
+; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
+; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 
 ; Test a case where %old really does need to be copied out of edx:eax.
 define internal void @test_atomic_cmpxchg_64_store(
     i32 %ret_iptr, i32 %iptr, i64 %expected, i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
                                                 i64 %desired, i32 6, i32 6)
   %__6 = inttoptr i32 %ret_iptr to i64*
   store i64 %old, i64* %__6, align 1
   ret void
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64_store
 ; CHECK: push ebx
 ; CHECK-DAG: mov edx
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
 ; CHECK-DAG: mov {{.*}},edx
 ; CHECK-DAG: mov {{.*}},eax
 ; ARM32-LABEL: test_atomic_cmpxchg_64_store
 ; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32: mov
-; ARM32: mov
-; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: cmpeq
+; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
+; ARM32: cmp [[V0]], {{r[0-9]+}}
+; ARM32: cmpeq [[V1]], {{r[0-9]+}}
+; ARM32: movne [[SUCCESS:r[0-9]+]],
+; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
+; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 ; ARM32: str
 ; ARM32: str
 
 ; Test with some more register pressure. When we have an alloca, ebp is
 ; used to manage the stack frame, so it cannot be used as a register either.
 define internal i64 @test_atomic_cmpxchg_64_alloca(i32 %iptr, i64 %expected,
                                                    i64 %desired) {
 entry:
@@ skipping 19 matching lines @@
 ; CHECK-DAG: mov ebx
 ; Ptr cannot be eax, ebx, ecx, or edx (used up for the expected and desired).
 ; It also cannot be ebp since we use that for alloca. Also make sure it's
 ; not esp, since that's the stack pointer and mucking with it will break
 ; the later use_ptr function call.
 ; That pretty much leaves esi, or edi as the only viable registers.
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{[ds]}}i]
 ; CHECK: call {{.*}} R_{{.*}} use_ptr
 ; ARM32-LABEL: test_atomic_cmpxchg_64_alloca
 ; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32: mov
-; ARM32: mov
-; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: cmpeq
+; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
+; ARM32: cmp [[V0]], {{r[0-9]+}}
+; ARM32: cmpeq [[V1]], {{r[0-9]+}}
+; ARM32: movne [[SUCCESS:r[0-9]+]],
+; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
+; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i32 @test_atomic_cmpxchg_32_ignored(i32 %iptr, i32 %expected,
                                                     i32 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
                                                     i32 %desired, i32 6, i32 6)
   ret i32 0
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_32_ignored
 ; CHECK: mov eax,{{.*}}
 ; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
 ; ARM32-LABEL: test_atomic_cmpxchg_32_ignored
 ; ARM32: dmb
-; ARM32: ldrex
-; ARM32: cmp
-; ARM32: strexeq
-; ARM32: cmpeq
+; ARM32: ldrex [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
+; ARM32: cmp [[V]], {{r[0-9]+}}
+; ARM32: movne [[SUCCESS:r[0-9]+]],
+; ARM32: strexeq [[SUCCESS]]
+; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 
 define internal i64 @test_atomic_cmpxchg_64_ignored(i32 %iptr, i64 %expected,
                                                     i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %ignored = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
                                                     i64 %desired, i32 6, i32 6)
   ret i64 0
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64_ignored
 ; CHECK: push ebx
 ; CHECK-DAG: mov edx
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
 ; ARM32-LABEL: test_atomic_cmpxchg_64_ignored
 ; ARM32: dmb
-; ARM32: ldrexd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
-; ARM32: cmp
-; ARM32-NEXT: cmpeq
-; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32O2-NOT: {{str|mov}}ne [[R0]]
-; ARM32O2-NOT: {{str|mov}}ne [[R1]]
-; ARM32: cmpeq
+; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
+; ARM32: cmp [[V0]], {{r[0-9]+}}
+; ARM32: cmpeq [[V1]], {{r[0-9]+}}
+; ARM32: movne [[SUCCESS:r[0-9]+]],
+; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
+; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 
 ;;;; Fence and is-lock-free.
 
 define internal void @test_atomic_fence() {
 entry:
   call void @llvm.nacl.atomic.fence(i32 6)
   ret void
 }
@@ skipping 157 matching lines @@
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_cmpxchg8b_regalloc
 ;;; eax and some other register will be used in the cmpxchg instruction.
 ; O2: lock cmpxchg8b QWORD PTR
 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable.
 ; O2-NOT: {{eax|ecx|edx|ebx}}
 ; O2: pop ebx