[wasm] Int64Lowering of I64ShrU and I64ShrS on ia32.

src/compiler/ia32/code-generator-ia32.cc

Index: src/compiler/ia32/code-generator-ia32.cc
diff --git a/src/compiler/ia32/code-generator-ia32.cc b/src/compiler/ia32/code-generator-ia32.cc
index 482376d6aa15851c9e2b32ce6f6706e513475324..dcbac2d406d7076736f90e912c5e0f46d94b5eb4 100644
--- a/src/compiler/ia32/code-generator-ia32.cc
+++ b/src/compiler/ia32/code-generator-ia32.cc
@@ -680,12 +680,28 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
         __ sar_cl(i.OutputOperand());
       }
       break;
-    case kIA32PairShl:
+    case kIA32ShlPair:
       if (HasImmediateInput(instr, 2)) {
-        __ PairShl(i.InputRegister(1), i.InputRegister(0), i.InputInt6(2));
+        __ ShlPair(i.InputRegister(1), i.InputRegister(0), i.InputInt6(2));
       } else {
         // Shift has been loaded into CL by the register allocator.
-        __ PairShl_cl(i.InputRegister(1), i.InputRegister(0));
+        __ ShlPair_cl(i.InputRegister(1), i.InputRegister(0));
+      }
+      break;
+    case kIA32ShrPair:
+      if (HasImmediateInput(instr, 2)) {
+        __ ShrPair(i.InputRegister(1), i.InputRegister(0), i.InputInt6(2));
+      } else {
+        // Shift has been loaded into CL by the register allocator.
+        __ ShrPair_cl(i.InputRegister(1), i.InputRegister(0));
+      }
+      break;
+    case kIA32SarPair:
+      if (HasImmediateInput(instr, 2)) {
+        __ SarPair(i.InputRegister(1), i.InputRegister(0), i.InputInt6(2));
+      } else {
+        // Shift has been loaded into CL by the register allocator.
+        __ SarPair_cl(i.InputRegister(1), i.InputRegister(0));
       }
       break;
     case kIA32Ror: