[wasm] Int64Lowering of I64ShrU and I64ShrS on ia32.

src/compiler/ia32/code-generator-ia32.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 
 #include "src/ast/scopes.h"
 #include "src/compiler/code-generator-impl.h"
 #include "src/compiler/gap-resolver.h"
 #include "src/compiler/node-matchers.h"
@@ skipping 670 matching lines @@
       }
       break;
     case kIA32PairShl:
       if (HasImmediateInput(instr, 2)) {
         __ PairShl(i.InputRegister(1), i.InputRegister(0), i.InputInt6(2));
       } else {
         // Shift has been loaded into CL by the register allocator.
         __ PairShl_cl(i.InputRegister(1), i.InputRegister(0));
       }
       break;
+    case kIA32PairShr:
+      if (HasImmediateInput(instr, 2)) {
+        __ PairShr(i.InputRegister(1), i.InputRegister(0), i.InputInt6(2));
+      } else {
+        // Shift has been loaded into CL by the register allocator.
+        __ PairShr_cl(i.InputRegister(1), i.InputRegister(0));
+      }
+      break;
+    case kIA32PairSar:
+      if (HasImmediateInput(instr, 2)) {
+        __ PairSar(i.InputRegister(1), i.InputRegister(0), i.InputInt6(2));
+      } else {
+        // Shift has been loaded into CL by the register allocator.
+        __ PairSar_cl(i.InputRegister(1), i.InputRegister(0));
+      }
+      break;
     case kIA32Ror:
       if (HasImmediateInput(instr, 1)) {
         __ ror(i.OutputOperand(), i.InputInt5(1));
       } else {
         __ ror_cl(i.OutputOperand());
       }
       break;
     case kIA32Lzcnt:
       __ Lzcnt(i.OutputRegister(), i.InputOperand(0));
       break;
@@ skipping 1110 matching lines @@
     int padding_size = last_lazy_deopt_pc_ + space_needed - current_pc;
     __ Nop(padding_size);
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8