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Side by Side Diff: src/mips/macro-assembler-mips.cc

Issue 1766323002: [mips] Mask ror immediates. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 9 months ago
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1 1
2 // Copyright 2012 the V8 project authors. All rights reserved. 2 // Copyright 2012 the V8 project authors. All rights reserved.
3 // Use of this source code is governed by a BSD-style license that can be 3 // Use of this source code is governed by a BSD-style license that can be
4 // found in the LICENSE file. 4 // found in the LICENSE file.
5 5
6 #include <limits.h> // For LONG_MIN, LONG_MAX. 6 #include <limits.h> // For LONG_MIN, LONG_MAX.
7 7
8 #if V8_TARGET_ARCH_MIPS 8 #if V8_TARGET_ARCH_MIPS
9 9
10 #include "src/base/bits.h" 10 #include "src/base/bits.h"
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1071 } 1071 }
1072 } 1072 }
1073 } 1073 }
1074 1074
1075 1075
1076 void MacroAssembler::Ror(Register rd, Register rs, const Operand& rt) { 1076 void MacroAssembler::Ror(Register rd, Register rs, const Operand& rt) {
1077 if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) { 1077 if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
1078 if (rt.is_reg()) { 1078 if (rt.is_reg()) {
1079 rotrv(rd, rs, rt.rm()); 1079 rotrv(rd, rs, rt.rm());
1080 } else { 1080 } else {
1081 rotr(rd, rs, rt.imm32_); 1081 rotr(rd, rs, rt.imm32_ & 0x1f);
1082 } 1082 }
1083 } else { 1083 } else {
1084 if (rt.is_reg()) { 1084 if (rt.is_reg()) {
1085 subu(at, zero_reg, rt.rm()); 1085 subu(at, zero_reg, rt.rm());
1086 sllv(at, rs, at); 1086 sllv(at, rs, at);
1087 srlv(rd, rs, rt.rm()); 1087 srlv(rd, rs, rt.rm());
1088 or_(rd, rd, at); 1088 or_(rd, rd, at);
1089 } else { 1089 } else {
1090 if (rt.imm32_ == 0) { 1090 if (rt.imm32_ == 0) {
1091 srl(rd, rs, 0); 1091 srl(rd, rs, 0);
1092 } else { 1092 } else {
1093 srl(at, rs, rt.imm32_); 1093 srl(at, rs, rt.imm32_ & 0x1f);
1094 sll(rd, rs, (0x20 - rt.imm32_) & 0x1f); 1094 sll(rd, rs, (0x20 - (rt.imm32_ & 0x1f)) & 0x1f);
1095 or_(rd, rd, at); 1095 or_(rd, rd, at);
1096 } 1096 }
1097 } 1097 }
1098 } 1098 }
1099 } 1099 }
1100 1100
1101 1101
1102 void MacroAssembler::Pref(int32_t hint, const MemOperand& rs) { 1102 void MacroAssembler::Pref(int32_t hint, const MemOperand& rs) {
1103 if (IsMipsArchVariant(kLoongson)) { 1103 if (IsMipsArchVariant(kLoongson)) {
1104 lw(zero_reg, rs); 1104 lw(zero_reg, rs);
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5913 if (mag.shift > 0) sra(result, result, mag.shift); 5913 if (mag.shift > 0) sra(result, result, mag.shift);
5914 srl(at, dividend, 31); 5914 srl(at, dividend, 31);
5915 Addu(result, result, Operand(at)); 5915 Addu(result, result, Operand(at));
5916 } 5916 }
5917 5917
5918 5918
5919 } // namespace internal 5919 } // namespace internal
5920 } // namespace v8 5920 } // namespace v8
5921 5921
5922 #endif // V8_TARGET_ARCH_MIPS 5922 #endif // V8_TARGET_ARCH_MIPS
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