Subzero: Fix symbol name mangling. Make flags global.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 889 matching lines @@
   Variable *T = makeReg(IceType_i32);
   Context.insert<InstFakeDef>(T);
   Context.insert<InstFakeDef>(GotPtr, T);
 }
 
 IceString TargetARM32::createGotoffRelocation(const ConstantRelocatable *CR) {
   const IceString &CRName = CR->getName();
   const IceString CRGotoffName =
       "GOTOFF$" + Func->getFunctionName() + "$" + CRName;
   if (KnownGotoffs.count(CRGotoffName) == 0) {
-    auto *Global = VariableDeclaration::create(Ctx);
+    constexpr bool SuppressMangling = true;
+    auto *Global = VariableDeclaration::create(Ctx, SuppressMangling);
     Global->setIsConstant(true);
     Global->setName(CRName);
-    Global->setSuppressMangling();
 
-    auto *Gotoff = VariableDeclaration::create(Ctx);
+    auto *Gotoff = VariableDeclaration::create(Ctx, SuppressMangling);
     constexpr auto GotFixup = R_ARM_GOTOFF32;
     Gotoff->setIsConstant(true);
-    Gotoff->setName(CRGotoffName);
-    Gotoff->setSuppressMangling();
     Gotoff->addInitializer(VariableDeclaration::RelocInitializer::create(
         Global, {RelocOffset::create(Ctx, 0)}, GotFixup));
+    Gotoff->setName(CRGotoffName);
     Func->addGlobal(Gotoff);
     KnownGotoffs.emplace(CRGotoffName);
   }
   return CRGotoffName;
 }
 
 void TargetARM32::materializeGotAddr(CfgNode *Node) {
   if (SandboxingType != ST_Nonsfi) {
     return;
   }
@@ skipping 24 matching lines @@
   assert(DefGotPtr->getSrcSize() == 1);
   auto *T = llvm::cast<Variable>(DefGotPtr->getSrc(0));
   loadNamedConstantRelocatablePIC(GlobalOffsetTable, T,
                                   [this, T](Variable *PC) { _add(T, PC, T); });
   _mov(GotPtr, T);
   DefGotPtr->setDeleted();
 }
 
 void TargetARM32::loadNamedConstantRelocatablePIC(
     const IceString &Name, Variable *Register,
-    std::function<void(Variable *PC)> Finish, bool SuppressMangling) {
+    std::function<void(Variable *PC)> Finish) {
   assert(SandboxingType == ST_Nonsfi);
   // We makeReg() here instead of getPhysicalRegister() because the latter ends
   // up creating multi-blocks temporaries that liveness fails to validate.
   auto *PC = makeReg(IceType_i32, RegARM32::Reg_pc);
 
   auto *AddPcReloc = RelocOffset::create(Ctx);
   AddPcReloc->setSubtract(true);
   auto *AddPcLabel = InstARM32Label::create(Func, this);
   AddPcLabel->setRelocOffset(AddPcReloc);
 
-  const IceString EmitText = Name;
-
   auto *MovwReloc = RelocOffset::create(Ctx);
   auto *MovwLabel = InstARM32Label::create(Func, this);
   MovwLabel->setRelocOffset(MovwReloc);
 
   auto *MovtReloc = RelocOffset::create(Ctx);
   auto *MovtLabel = InstARM32Label::create(Func, this);
   MovtLabel->setRelocOffset(MovtReloc);
 
   // The EmitString for these constant relocatables have hardcoded offsets
   // attached to them. This could be dangerous if, e.g., we ever implemented
   // instruction scheduling but llvm-mc currently does not support
   //
   //   movw reg, #:lower16:(Symbol - Label - Number)
   //   movt reg, #:upper16:(Symbol - Label - Number)
   //
   // relocations.
   static constexpr RelocOffsetT PcOffset = -8;
   auto *CRLower = Ctx->getConstantSym(PcOffset, {MovwReloc, AddPcReloc}, Name,
-                                      EmitText + " -16", SuppressMangling);
+                                      Name + " -16");
   auto *CRUpper = Ctx->getConstantSym(PcOffset, {MovtReloc, AddPcReloc}, Name,
-                                      EmitText + " -12", SuppressMangling);
+                                      Name + " -12");
 
   Context.insert(MovwLabel);
   _movw(Register, CRLower);
   Context.insert(MovtLabel);
   _movt(Register, CRUpper);
   // PC = fake-def to keep liveness consistent.
   Context.insert<InstFakeDef>(PC);
   Context.insert(AddPcLabel);
   Finish(PC);
 }
@@ skipping 4957 matching lines @@
         // because ARM does not have a veor instruction with S registers.
         Variable *T = makeReg(IceType_f64, RegNum);
         Context.insert<InstFakeDef>(T);
         _veor(T, T, T);
         return T;
       }
 
       // Load floats/doubles from literal pool.
       std::string Buffer;
       llvm::raw_string_ostream StrBuf(Buffer);
-      llvm::cast<Constant>(From)->emitPoolLabel(StrBuf, Ctx);
+      llvm::cast<Constant>(From)->emitPoolLabel(StrBuf);
       llvm::cast<Constant>(From)->setShouldBePooled(true);
-      Constant *Offset = Ctx->getConstantSym(0, StrBuf.str(), true);
+      Constant *Offset = Ctx->getConstantSym(0, StrBuf.str());
       Variable *BaseReg = nullptr;
       if (SandboxingType == ST_Nonsfi) {
         // vldr does not support the [base, index] addressing mode, so we need
         // to legalize Offset to a register. Otherwise, we could simply
         //   vldr dest, [got, reg(Offset)]
         BaseReg = legalizeToReg(Offset);
       } else {
         BaseReg = makeReg(getPointerType());
         _movw(BaseReg, Offset);
         _movt(BaseReg, Offset);
@@ skipping 761 matching lines @@
     static_assert(sizeof(double) == sizeof(uint64_t),
                   "Double should be 8 bytes.");
     return Utils::bitCopy<uint64_t>(Value);
   }
 };
 const char ConstantPoolEmitterTraits<double>::AsmTag[] = ".quad";
 const char ConstantPoolEmitterTraits<double>::TypeName[] = "f64";
 
 template <typename T>
 void emitConstant(
-    Ostream &Str, const GlobalContext *Ctx,
+    Ostream &Str,
     const typename ConstantPoolEmitterTraits<T>::ConstantType *Const) {
   using Traits = ConstantPoolEmitterTraits<T>;
-  Const->emitPoolLabel(Str, Ctx);
+  Const->emitPoolLabel(Str);
   Str << ":\n\t" << Traits::AsmTag << "\t0x";
   T Value = Const->getValue();
   Str.write_hex(Traits::bitcastToUint64(Value));
   Str << "\t/* " << Traits::TypeName << " " << Value << " */\n";
 }
 
 template <typename T> void emitConstantPool(GlobalContext *Ctx) {
   if (!BuildDefs::dump()) {
     return;
   }
@@ skipping 12 matching lines @@
   if (Ctx->getFlags().shouldReorderPooledConstants()) {
     // TODO(jpp): add constant pooling.
     UnimplementedError(Ctx->getFlags());
   }
 
   for (Constant *C : Pool) {
     if (!C->getShouldBePooled()) {
       continue;
     }
 
-    emitConstant<T>(Str, Ctx, llvm::dyn_cast<typename Traits::ConstantType>(C));
+    emitConstant<T>(Str, llvm::dyn_cast<typename Traits::ConstantType>(C));
   }
 }
 } // end of anonymous namespace
 
 void TargetDataARM32::lowerConstants() {
   if (Ctx->getFlags().getDisableTranslation())
     return;
   switch (Ctx->getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
@@ skipping 77 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice