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| 1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// |
| 2 // | 2 // |
| 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
| 5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
| 6 // | 6 // |
| 7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
| 8 // | 8 // |
| 9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
| 10 // | 10 // |
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| 589 const Assembler &Asm) const { | 589 const Assembler &Asm) const { |
| 590 if (!BuildDefs::dump()) | 590 if (!BuildDefs::dump()) |
| 591 return InstARM32::InstSize; | 591 return InstARM32::InstSize; |
| 592 Ostream &Str = Ctx->getStrEmit(); | 592 Ostream &Str = Ctx->getStrEmit(); |
| 593 IValueT Inst = Asm.load<IValueT>(position()); | 593 IValueT Inst = Asm.load<IValueT>(position()); |
| 594 const bool IsMovw = kind() == llvm::ELF::R_ARM_MOVW_ABS_NC || | 594 const bool IsMovw = kind() == llvm::ELF::R_ARM_MOVW_ABS_NC || |
| 595 kind() == llvm::ELF::R_ARM_MOVW_PREL_NC; | 595 kind() == llvm::ELF::R_ARM_MOVW_PREL_NC; |
| 596 Str << "\t" | 596 Str << "\t" |
| 597 "mov" << (IsMovw ? "w" : "t") << "\t" | 597 "mov" << (IsMovw ? "w" : "t") << "\t" |
| 598 << RegARM32::getRegName(RegNumT::fixme((Inst >> kRdShift) & 0xF)) | 598 << RegARM32::getRegName(RegNumT::fixme((Inst >> kRdShift) & 0xF)) |
| 599 << ", #:" << (IsMovw ? "lower" : "upper") << "16:" << symbol(Ctx, &Asm) | 599 << ", #:" << (IsMovw ? "lower" : "upper") << "16:" << symbol(&Asm) |
| 600 << "\t@ .word " << llvm::format_hex_no_prefix(Inst, 8) << "\n"; | 600 << "\t@ .word " << llvm::format_hex_no_prefix(Inst, 8) << "\n"; |
| 601 return InstARM32::InstSize; | 601 return InstARM32::InstSize; |
| 602 } | 602 } |
| 603 | 603 |
| 604 IValueT AssemblerARM32::encodeElmtType(Type ElmtTy) { | 604 IValueT AssemblerARM32::encodeElmtType(Type ElmtTy) { |
| 605 switch (ElmtTy) { | 605 switch (ElmtTy) { |
| 606 case IceType_i8: | 606 case IceType_i8: |
| 607 return 0; | 607 return 0; |
| 608 case IceType_i16: | 608 case IceType_i16: |
| 609 return 1; | 609 return 1; |
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| 643 return F; | 643 return F; |
| 644 } | 644 } |
| 645 | 645 |
| 646 size_t BlRelocatableFixup::emit(GlobalContext *Ctx, | 646 size_t BlRelocatableFixup::emit(GlobalContext *Ctx, |
| 647 const Assembler &Asm) const { | 647 const Assembler &Asm) const { |
| 648 if (!BuildDefs::dump()) | 648 if (!BuildDefs::dump()) |
| 649 return InstARM32::InstSize; | 649 return InstARM32::InstSize; |
| 650 Ostream &Str = Ctx->getStrEmit(); | 650 Ostream &Str = Ctx->getStrEmit(); |
| 651 IValueT Inst = Asm.load<IValueT>(position()); | 651 IValueT Inst = Asm.load<IValueT>(position()); |
| 652 Str << "\t" | 652 Str << "\t" |
| 653 "bl\t" << symbol(Ctx, &Asm) << "\t@ .word " | 653 "bl\t" << symbol(&Asm) << "\t@ .word " |
| 654 << llvm::format_hex_no_prefix(Inst, 8) << "\n"; | 654 << llvm::format_hex_no_prefix(Inst, 8) << "\n"; |
| 655 return InstARM32::InstSize; | 655 return InstARM32::InstSize; |
| 656 } | 656 } |
| 657 | 657 |
| 658 void BlRelocatableFixup::emitOffset(Assembler *Asm) const { | 658 void BlRelocatableFixup::emitOffset(Assembler *Asm) const { |
| 659 // cccc101liiiiiiiiiiiiiiiiiiiiiiii where cccc=Cond, l=Link, and | 659 // cccc101liiiiiiiiiiiiiiiiiiiiiiii where cccc=Cond, l=Link, and |
| 660 // iiiiiiiiiiiiiiiiiiiiiiii= | 660 // iiiiiiiiiiiiiiiiiiiiiiii= |
| 661 // EncodedBranchOffset(cccc101l000000000000000000000000, Offset); | 661 // EncodedBranchOffset(cccc101l000000000000000000000000, Offset); |
| 662 const IValueT Inst = Asm->load<IValueT>(position()); | 662 const IValueT Inst = Asm->load<IValueT>(position()); |
| 663 constexpr IValueT OffsetMask = 0x00FFFFFF; | 663 constexpr IValueT OffsetMask = 0x00FFFFFF; |
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| 3196 constexpr const char *Vsqrts = "vsqrts"; | 3196 constexpr const char *Vsqrts = "vsqrts"; |
| 3197 IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts); | 3197 IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts); |
| 3198 IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts); | 3198 IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts); |
| 3199 constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6; | 3199 constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6; |
| 3200 constexpr IValueT S0 = 0; | 3200 constexpr IValueT S0 = 0; |
| 3201 emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm); | 3201 emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm); |
| 3202 } | 3202 } |
| 3203 | 3203 |
| 3204 } // end of namespace ARM32 | 3204 } // end of namespace ARM32 |
| 3205 } // end of namespace Ice | 3205 } // end of namespace Ice |
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