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Side by Side Diff: src/compiler/arm/instruction-codes-arm.h

Issue 1765973002: [turbofan] Implementation of Word32PairShl on arm. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@wasm-shift
Patch Set: Rebase. Created 4 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 28 matching lines...) Expand all
39 V(ArmSbfx) \ 39 V(ArmSbfx) \
40 V(ArmSxtb) \ 40 V(ArmSxtb) \
41 V(ArmSxth) \ 41 V(ArmSxth) \
42 V(ArmSxtab) \ 42 V(ArmSxtab) \
43 V(ArmSxtah) \ 43 V(ArmSxtah) \
44 V(ArmUxtb) \ 44 V(ArmUxtb) \
45 V(ArmUxth) \ 45 V(ArmUxth) \
46 V(ArmUxtab) \ 46 V(ArmUxtab) \
47 V(ArmRbit) \ 47 V(ArmRbit) \
48 V(ArmUxtah) \ 48 V(ArmUxtah) \
49 V(ArmPairLsl) \
49 V(ArmVcmpF32) \ 50 V(ArmVcmpF32) \
50 V(ArmVaddF32) \ 51 V(ArmVaddF32) \
51 V(ArmVsubF32) \ 52 V(ArmVsubF32) \
52 V(ArmVmulF32) \ 53 V(ArmVmulF32) \
53 V(ArmVmlaF32) \ 54 V(ArmVmlaF32) \
54 V(ArmVmlsF32) \ 55 V(ArmVmlsF32) \
55 V(ArmVdivF32) \ 56 V(ArmVdivF32) \
56 V(ArmVabsF32) \ 57 V(ArmVabsF32) \
57 V(ArmVnegF32) \ 58 V(ArmVnegF32) \
58 V(ArmVsqrtF32) \ 59 V(ArmVsqrtF32) \
(...skipping 63 matching lines...) Expand 10 before | Expand all | Expand 10 after
122 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 123 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
123 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 124 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
124 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 125 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
125 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ 126 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
126 127
127 } // namespace compiler 128 } // namespace compiler
128 } // namespace internal 129 } // namespace internal
129 } // namespace v8 130 } // namespace v8
130 131
131 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 132 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
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