[turbofan] Implementation of Word32PairShl on arm.

src/arm/macro-assembler-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #if V8_TARGET_ARCH_ARM
 
 #include "src/base/bits.h"
 #include "src/base/division-by-constant.h"
@@ skipping 1038 matching lines @@
 
 
 void MacroAssembler::VmovLow(DwVfpRegister dst, Register src) {
   if (dst.code() < 16) {
     const LowDwVfpRegister loc = LowDwVfpRegister::from_code(dst.code());
     vmov(loc.low(), src);
   } else {
     vmov(dst, VmovIndexLo, src);
   }
 }
+void MacroAssembler::PairLsl(Register dst_low, Register dst_high,
+                             Register src_low, Register src_high,
+                             Register scratch, Register shift) {
+  Label less_than_32;

[martyn.capewell, 2016/03/04 18:54:57]

Add some register alias assertions: perhaps !AreAliased() for all input
registers makes reasoning easier, but it may be helpful to allow dst_low ==
src_low and dst_high == src_high.

[ahaas, 2016/03/07 13:40:49]

I enforced src_low == dst_low now in the register allocator now, and I allow
src_high == dst_high.
I added !AreAliased() checks for (dst_low, src_high) and (dst_high, src_low).

+  Label done;
+  cmp_raw_immediate(shift, 32);
+  b(lt, &less_than_32);
+  eor(dst_low, dst_low, Operand(dst_low));

[martyn.capewell, 2016/03/04 18:54:57]

mov(dst_low, Operand(0))

[martyn.capewell, 2016/03/04 18:54:57]

Switching zero and shift operations here would allow dst_low to alias src_low.

[ahaas, 2016/03/07 13:40:48]

Done.

+  and_(scratch, shift, Operand(0x1f));
+  lsl(dst_high, src_low, Operand(scratch));
+  jmp(&done);
+  bind(&less_than_32);
+  rsb(scratch, shift, Operand(32));
+  lsr(dst_low, src_low, Operand(scratch));
+  lsl(dst_high, src_high, Operand(shift));
+  orr(dst_high, dst_high, dst_low);
+  lsl(dst_low, src_low, Operand(shift));

[martyn.capewell, 2016/03/04 18:54:57]

You can combine shift with orr here:
  lsl(dst_high, src_high, Operand(shift);
  orr(dst_high, dst_high, Operand(src_low, LSR, scratch));
  lsl(dst_low, src_low, Operand(shift));

[ahaas, 2016/03/07 13:40:48]

Thanks, that's really helpful.

+  bind(&done);
+}
 
+void MacroAssembler::PairLsl(Register dst_low, Register dst_high,
+                             Register src_low, Register src_high,
+                             Register scratch, uint32_t shift) {

[martyn.capewell, 2016/03/04 18:54:57]

scratch isn't used.

[ahaas, 2016/03/07 13:40:49]

I removed it.

+  Label less_than_32;

[martyn.capewell, 2016/03/04 18:54:57]

Add some register alias assertions. At the top level, I think (dst_low !=
dst_high) && (src_low != src_high) is enough.

[ahaas, 2016/03/07 13:40:49]

Done.

+  Label done;
+  if (shift >= 32) {

[martyn.capewell, 2016/03/04 18:54:57]

Switch the zero and shift instructions here, so dst_low can alias src_low.

[ahaas, 2016/03/07 13:40:49]

Done.

+    eor(dst_low, dst_low, Operand(dst_low));

[martyn.capewell, 2016/03/04 18:54:57]

mov(dst_low, Operand(0))

[ahaas, 2016/03/07 13:40:48]

Done.

+    shift &= 0x1f;
+    lsl(dst_high, src_low, Operand(shift));
+  } else if (shift == 0) {

[martyn.capewell, 2016/03/04 18:54:57]

Assert dst_low != src_high.

+    mov(dst_low, src_low);

[martyn.capewell, 2016/03/04 18:54:57]

Use Move() here to eliminate redundant instructions when dst == src.

[ahaas, 2016/03/07 13:40:49]

Aha, that's useful. Thanks.

+    mov(dst_high, src_high);
+  } else {
+    lsr(dst_low, src_low, Operand(32 - shift));
+    lsl(dst_high, src_high, Operand(shift));
+    orr(dst_high, dst_high, dst_low);
+    lsl(dst_low, src_low, Operand(shift));

[martyn.capewell, 2016/03/04 18:54:57]

Combine shift with orr:
  lsl(dst_high, src_high, Operand(shift);
  orr(dst_high, dst_high, Operand(src_low, LSR, 32 - shift));
  lsl(dst_low, src_low, Operand(shift));

Also, assert (dst_high != src_low) && (src_high != dst_low).

[ahaas, 2016/03/07 13:40:48]

Done.

+  }
+}
 
 void MacroAssembler::LoadConstantPoolPointerRegisterFromCodeTargetAddress(
     Register code_target_address) {
   DCHECK(FLAG_enable_embedded_constant_pool);
   ldr(pp, MemOperand(code_target_address,
                      Code::kConstantPoolOffset - Code::kHeaderSize));
   add(pp, pp, code_target_address);
 }
 
 
@@ skipping 2618 matching lines @@
     }
   }
   if (mag.shift > 0) mov(result, Operand(result, ASR, mag.shift));
   add(result, result, Operand(dividend, LSR, 31));
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_ARM