[turbofan] SSA Validation

src/compiler/instruction.cc

Index: src/compiler/instruction.cc
diff --git a/src/compiler/instruction.cc b/src/compiler/instruction.cc
index 05c6215c74c569d40aef8867c0f9010dc25ca85c..5eb0d88bb2bf5064e70c0eba7a236f60ee7a4e5d 100644
--- a/src/compiler/instruction.cc
+++ b/src/compiler/instruction.cc
@@ -620,7 +620,7 @@ InstructionBlocks* InstructionSequence::InstructionBlocksFor(
   return blocks;
 }
 
-void InstructionSequence::Validate() {
+void InstructionSequence::ValidateEdgeSplitForm() {
   // Validate blocks are in edge-split form: no block with multiple successors
   // has an edge to a block (== a successor) with more than one predecessors.
   for (const InstructionBlock* block : instruction_blocks()) {
@@ -635,6 +635,21 @@ void InstructionSequence::Validate() {
   }
 }
 
+void InstructionSequence::ValidateSSA() {
+  // TODO(mtrofin): We could use a local zone here instead.
+  BitVector definitions(VirtualRegisterCount(), zone());
+  for (const Instruction* instruction : *this) {
+    for (size_t i = 0; i < instruction->OutputCount(); ++i) {
+      const InstructionOperand* output = instruction->OutputAt(i);
+      int vreg = (output->IsConstant())
+                     ? ConstantOperand::cast(output)->virtual_register()
+                     : UnallocatedOperand::cast(output)->virtual_register();
+      CHECK(!definitions.Contains(vreg));
+      definitions.Add(vreg);
+    }
+  }
+}
+
 void InstructionSequence::ComputeAssemblyOrder(InstructionBlocks* blocks) {
   int ao = 0;
   for (InstructionBlock* const block : *blocks) {
@@ -669,7 +684,7 @@ InstructionSequence::InstructionSequence(Isolate* isolate,
   block_starts_.reserve(instruction_blocks_->size());
 
 #if DEBUG
-  Validate();
+  ValidateEdgeSplitForm();
 #endif
 }