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| 1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
| 6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
| 7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
| 8 // | 8 // |
| 9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
| 10 // | 10 // |
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| 1397 } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) { | 1397 } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) { |
| 1398 if (instr->SzValue() == 0x1) { | 1398 if (instr->SzValue() == 0x1) { |
| 1399 Format(instr, "vsqrt'cond.f64 'Dd, 'Dm"); | 1399 Format(instr, "vsqrt'cond.f64 'Dd, 'Dm"); |
| 1400 } else { | 1400 } else { |
| 1401 Format(instr, "vsqrt'cond.f32 'Sd, 'Sm"); | 1401 Format(instr, "vsqrt'cond.f32 'Sd, 'Sm"); |
| 1402 } | 1402 } |
| 1403 } else if (instr->Opc3Value() == 0x0) { | 1403 } else if (instr->Opc3Value() == 0x0) { |
| 1404 if (instr->SzValue() == 0x1) { | 1404 if (instr->SzValue() == 0x1) { |
| 1405 Format(instr, "vmov'cond.f64 'Dd, 'd"); | 1405 Format(instr, "vmov'cond.f64 'Dd, 'd"); |
| 1406 } else { | 1406 } else { |
| 1407 Unknown(instr); // Not used by V8. | 1407 Format(instr, "vmov'cond.f32 'Sd, 'd"); |
| 1408 } | 1408 } |
| 1409 } else if (((instr->Opc2Value() == 0x6)) && instr->Opc3Value() == 0x3) { | 1409 } else if (((instr->Opc2Value() == 0x6)) && instr->Opc3Value() == 0x3) { |
| 1410 // vrintz - round towards zero (truncate) | 1410 // vrintz - round towards zero (truncate) |
| 1411 if (instr->SzValue() == 0x1) { | 1411 if (instr->SzValue() == 0x1) { |
| 1412 Format(instr, "vrintz'cond.f64.f64 'Dd, 'Dm"); | 1412 Format(instr, "vrintz'cond.f64.f64 'Dd, 'Dm"); |
| 1413 } else { | 1413 } else { |
| 1414 Format(instr, "vrintz'cond.f32.f32 'Sd, 'Sm"); | 1414 Format(instr, "vrintz'cond.f32.f32 'Sd, 'Sm"); |
| 1415 } | 1415 } |
| 1416 } else { | 1416 } else { |
| 1417 Unknown(instr); // Not used by V8. | 1417 Unknown(instr); // Not used by V8. |
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| 2008 v8::internal::PrintF( | 2008 v8::internal::PrintF( |
| 2009 f, "%p %08x %s\n", | 2009 f, "%p %08x %s\n", |
| 2010 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 2010 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
| 2011 } | 2011 } |
| 2012 } | 2012 } |
| 2013 | 2013 |
| 2014 | 2014 |
| 2015 } // namespace disasm | 2015 } // namespace disasm |
| 2016 | 2016 |
| 2017 #endif // V8_TARGET_ARCH_ARM | 2017 #endif // V8_TARGET_ARCH_ARM |
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