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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <assert.h> | 5 #include <assert.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdio.h> | 7 #include <stdio.h> |
8 | 8 |
9 #if V8_TARGET_ARCH_IA32 | 9 #if V8_TARGET_ARCH_IA32 |
10 | 10 |
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1211 return 2; | 1211 return 2; |
1212 } | 1212 } |
1213 | 1213 |
1214 | 1214 |
1215 // Mnemonics for instructions 0xF0 byte. | 1215 // Mnemonics for instructions 0xF0 byte. |
1216 // Returns NULL if the instruction is not handled here. | 1216 // Returns NULL if the instruction is not handled here. |
1217 static const char* F0Mnem(byte f0byte) { | 1217 static const char* F0Mnem(byte f0byte) { |
1218 switch (f0byte) { | 1218 switch (f0byte) { |
1219 case 0x0B: | 1219 case 0x0B: |
1220 return "ud2"; | 1220 return "ud2"; |
1221 case 0x18: return "prefetch"; | 1221 case 0x18: |
1222 case 0xA2: return "cpuid"; | 1222 return "prefetch"; |
1223 case 0xBE: return "movsx_b"; | 1223 case 0xA2: |
1224 case 0xBF: return "movsx_w"; | 1224 return "cpuid"; |
1225 case 0xB6: return "movzx_b"; | 1225 case 0xBE: |
1226 case 0xB7: return "movzx_w"; | 1226 return "movsx_b"; |
1227 case 0xAF: return "imul"; | 1227 case 0xBF: |
1228 case 0xA5: return "shld"; | 1228 return "movsx_w"; |
1229 case 0xAD: return "shrd"; | 1229 case 0xB6: |
1230 case 0xAC: return "shrd"; // 3-operand version. | 1230 return "movzx_b"; |
1231 case 0xAB: return "bts"; | 1231 case 0xB7: |
| 1232 return "movzx_w"; |
| 1233 case 0xAF: |
| 1234 return "imul"; |
| 1235 case 0xA4: |
| 1236 return "shld"; |
| 1237 case 0xA5: |
| 1238 return "shld"; |
| 1239 case 0xAD: |
| 1240 return "shrd"; |
| 1241 case 0xAC: |
| 1242 return "shrd"; // 3-operand version. |
| 1243 case 0xAB: |
| 1244 return "bts"; |
1232 case 0xBC: | 1245 case 0xBC: |
1233 return "bsf"; | 1246 return "bsf"; |
1234 case 0xBD: return "bsr"; | 1247 case 0xBD: |
| 1248 return "bsr"; |
1235 default: return NULL; | 1249 default: return NULL; |
1236 } | 1250 } |
1237 } | 1251 } |
1238 | 1252 |
1239 | 1253 |
1240 // Disassembled instruction '*instr' and writes it into 'out_buffer'. | 1254 // Disassembled instruction '*instr' and writes it into 'out_buffer'. |
1241 int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer, | 1255 int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer, |
1242 byte* instr) { | 1256 byte* instr) { |
1243 tmp_buffer_pos_ = 0; // starting to write as position 0 | 1257 tmp_buffer_pos_ = 0; // starting to write as position 0 |
1244 byte* data = instr; | 1258 byte* data = instr; |
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1463 } else if ((f0byte & 0xF0) == 0x80) { | 1477 } else if ((f0byte & 0xF0) == 0x80) { |
1464 data += JumpConditional(data, branch_hint); | 1478 data += JumpConditional(data, branch_hint); |
1465 } else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 || | 1479 } else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 || |
1466 f0byte == 0xB7 || f0byte == 0xAF) { | 1480 f0byte == 0xB7 || f0byte == 0xAF) { |
1467 data += 2; | 1481 data += 2; |
1468 data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data); | 1482 data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data); |
1469 } else if ((f0byte & 0xF0) == 0x90) { | 1483 } else if ((f0byte & 0xF0) == 0x90) { |
1470 data += SetCC(data); | 1484 data += SetCC(data); |
1471 } else if ((f0byte & 0xF0) == 0x40) { | 1485 } else if ((f0byte & 0xF0) == 0x40) { |
1472 data += CMov(data); | 1486 data += CMov(data); |
1473 } else if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) { | 1487 } else if (f0byte == 0xA4) { |
1474 // shrd, shld, bts | |
1475 data += 2; | 1488 data += 2; |
1476 AppendToBuffer("%s ", f0mnem); | 1489 AppendToBuffer("%s ", f0mnem); |
1477 int mod, regop, rm; | 1490 int mod, regop, rm; |
| 1491 get_modrm(*data, &mod, ®op, &rm); |
| 1492 int8_t imm8 = static_cast<int8_t>(data[1]); |
| 1493 data += 2; |
| 1494 AppendToBuffer("%s,%s,%d", NameOfCPURegister(rm), |
| 1495 NameOfCPURegister(regop), static_cast<int>(imm8)); |
| 1496 } else if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) { |
| 1497 // shrd, shld_cl, bts |
| 1498 data += 2; |
| 1499 AppendToBuffer("%s ", f0mnem); |
| 1500 int mod, regop, rm; |
1478 get_modrm(*data, &mod, ®op, &rm); | 1501 get_modrm(*data, &mod, ®op, &rm); |
1479 data += PrintRightOperand(data); | 1502 data += PrintRightOperand(data); |
1480 if (f0byte == 0xAB) { | 1503 if (f0byte == 0xAB) { |
1481 AppendToBuffer(",%s", NameOfCPURegister(regop)); | 1504 AppendToBuffer(",%s", NameOfCPURegister(regop)); |
1482 } else { | 1505 } else { |
1483 AppendToBuffer(",%s,cl", NameOfCPURegister(regop)); | 1506 AppendToBuffer(",%s,cl", NameOfCPURegister(regop)); |
1484 } | 1507 } |
1485 } else if (f0byte == 0xBC) { | 1508 } else if (f0byte == 0xBC) { |
1486 data += 2; | 1509 data += 2; |
1487 int mod, regop, rm; | 1510 int mod, regop, rm; |
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2259 fprintf(f, " "); | 2282 fprintf(f, " "); |
2260 } | 2283 } |
2261 fprintf(f, " %s\n", buffer.start()); | 2284 fprintf(f, " %s\n", buffer.start()); |
2262 } | 2285 } |
2263 } | 2286 } |
2264 | 2287 |
2265 | 2288 |
2266 } // namespace disasm | 2289 } // namespace disasm |
2267 | 2290 |
2268 #endif // V8_TARGET_ARCH_IA32 | 2291 #endif // V8_TARGET_ARCH_IA32 |
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