Subzero. ARM32. Fixes bugs uncovered by the llvm test suite.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 307 matching lines @@
   // minimal syntactic overhead, so that the lowering code can look as close to
   // assembly as practical.
   void _add(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Add>(Dest, Src0, Src1, Pred);
   }
   void _adds(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     constexpr bool SetFlags = true;
     Context.insert<InstARM32Add>(Dest, Src0, Src1, Pred, SetFlags);
+    if (SetFlags) {
+      Context.insert<InstFakeUse>(Dest);
+    }
   }
   void _adc(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Adc>(Dest, Src0, Src1, Pred);
   }
   void _and(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32And>(Dest, Src0, Src1, Pred);
   }
   void _asr(Variable *Dest, Variable *Src0, Operand *Src1,
@@ skipping 50 matching lines @@
     return Ldrex;
   }
   void _lsl(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Lsl>(Dest, Src0, Src1, Pred);
   }
   void _lsls(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     constexpr bool SetFlags = true;
     Context.insert<InstARM32Lsl>(Dest, Src0, Src1, Pred, SetFlags);
+    if (SetFlags) {
+      Context.insert<InstFakeUse>(Dest);
+    }
   }
   void _lsr(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Lsr>(Dest, Src0, Src1, Pred);
   }
   void _mla(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Mla>(Dest, Src0, Src1, Acc, Pred);
   }
   void _mls(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc,
@@ skipping 296 matching lines @@
     Context.insert<InstARM32Mvn>(Dest, Src0, Pred);
   }
   void _orr(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Orr>(Dest, Src0, Src1, Pred);
   }
   void _orrs(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     constexpr bool SetFlags = true;
     Context.insert<InstARM32Orr>(Dest, Src0, Src1, Pred, SetFlags);
+    if (SetFlags) {
+      Context.insert<InstFakeUse>(Dest);
+    }
   }
   void _push(const VarList &Sources) { Context.insert<InstARM32Push>(Sources); }
   void _pop(const VarList &Dests) {
     Context.insert<InstARM32Pop>(Dests);
     // Mark dests as modified.
     for (Variable *Dest : Dests)
       Context.insert<InstFakeDef>(Dest);
   }
   void _rbit(Variable *Dest, Variable *Src0,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Rbit>(Dest, Src0, Pred);
   }
   void _rev(Variable *Dest, Variable *Src0,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Rev>(Dest, Src0, Pred);
   }
   void _ret(Variable *LR, Variable *Src0 = nullptr) {
     Context.insert<InstARM32Ret>(LR, Src0);
   }
   void _rscs(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     constexpr bool SetFlags = true;
     Context.insert<InstARM32Rsc>(Dest, Src0, Src1, Pred, SetFlags);
+    if (SetFlags) {
+      Context.insert<InstFakeUse>(Dest);
+    }
   }
   void _rsc(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Rsc>(Dest, Src0, Src1, Pred);
   }
   void _rsbs(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     constexpr bool SetFlags = true;
     Context.insert<InstARM32Rsb>(Dest, Src0, Src1, Pred, SetFlags);
+    if (SetFlags) {
+      Context.insert<InstFakeUse>(Dest);
+    }
   }
   void _rsb(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Rsb>(Dest, Src0, Src1, Pred);
   }
   void _sbc(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Sbc>(Dest, Src0, Src1, Pred);
   }
   void _sbcs(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     constexpr bool SetFlags = true;
     Context.insert<InstARM32Sbc>(Dest, Src0, Src1, Pred, SetFlags);
+    if (SetFlags) {
+      Context.insert<InstFakeUse>(Dest);
+    }
   }
   void _sdiv(Variable *Dest, Variable *Src0, Variable *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Sdiv>(Dest, Src0, Src1, Pred);
   }
   /// _str, for all your Variable to memory transfers. Addr has the same
   /// restrictions that it does in _ldr.
   void _str(Variable *Value, OperandARM32Mem *Addr,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Str>(Value, Addr, Pred);
@@ skipping 12 matching lines @@
     Instr->setDestRedefined();
   }
   void _sub(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Sub>(Dest, Src0, Src1, Pred);
   }
   void _subs(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     constexpr bool SetFlags = true;
     Context.insert<InstARM32Sub>(Dest, Src0, Src1, Pred, SetFlags);
+    if (SetFlags) {
+      Context.insert<InstFakeUse>(Dest);
+    }
   }
   void _sxt(Variable *Dest, Variable *Src0,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Sxt>(Dest, Src0, Pred);
   }
   void _tst(Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Tst>(Src0, Src1, Pred);
   }
   void _trap() { Context.insert<InstARM32Trap>(); }
@@ skipping 509 matching lines @@
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H