Subzero. ARM32. Fixes bugs uncovered by the gcc torture tests.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Declares the TargetLoweringARM32 class, which implements the
 /// TargetLowering interface for the ARM 32-bit architecture.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICETARGETLOWERINGARM32_H
 #define SUBZERO_SRC_ICETARGETLOWERINGARM32_H
 
 #include "IceAssemblerARM32.h"
 #include "IceDefs.h"
 #include "IceInstARM32.h"
 #include "IceRegistersARM32.h"
 #include "IceTargetLowering.h"
 
+#include <utility>
+
 namespace Ice {
 namespace ARM32 {
 
 // Class encapsulating ARM cpu features / instruction set.
 class TargetARM32Features {
   TargetARM32Features() = delete;
   TargetARM32Features(const TargetARM32Features &) = delete;
   TargetARM32Features &operator=(const TargetARM32Features &) = delete;
 
 public:
@@ skipping 760 matching lines @@
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Tst>(Src0, Src1, Pred);
   }
   void _trap() { Context.insert<InstARM32Trap>(); }
   void _udiv(Variable *Dest, Variable *Src0, Variable *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Udiv>(Dest, Src0, Src1, Pred);
   }
   void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0,
               Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) {
+    // umull requires DestLo and DestHi to be assigned to different GPRs. The
+    // following lines create overlapping liveness ranges for both variables. If
+    // either one of them is live, then they are both going to be live, and thus
+    // assigned to different registers; if they are both dead, then DCE will
+    // kick in and delete the following three instructions.
+    Context.insert<InstFakeDef>(DestHi);
     Context.insert<InstARM32Umull>(DestLo, DestHi, Src0, Src1, Pred);
-    // Model the modification to the second dest as a fake def. Note that the
-    // def is not predicated.
-    Context.insert<InstFakeDef>(DestHi, DestLo);
+    Context.insert<InstFakeDef>(DestHi, DestLo)->setDestRedefined();
     Context.insert<InstFakeUse>(DestHi);
   }
   void _uxt(Variable *Dest, Variable *Src0,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Uxt>(Dest, Src0, Pred);
   }
   void _vabs(Variable *Dest, Variable *Src,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Vabs>(Dest, Src, Pred);
   }
@@ skipping 214 matching lines @@
     void strex(Variable *Dest, Variable *Src, OperandARM32Mem *Mem,
                CondARM32::Cond Pred);
 
     /// Decrements sp:
     ///
     ///   sub sp, sp, SubAmount
     ///   bic sp, sp, 0xc0000000
     void sub_sp(Operand *SubAmount);
 
   private:
-    AutoBundle Bundler;
-    TargetARM32 *Target;
+    TargetARM32 *const Target;
+    const InstBundleLock::Option BundleOption;
+    std::unique_ptr<AutoBundle> Bundler;
+
+    void createAutoBundle();
   };
 
   class PostLoweringLegalizer {
     PostLoweringLegalizer() = delete;
     PostLoweringLegalizer(const PostLoweringLegalizer &) = delete;
     PostLoweringLegalizer &operator=(const PostLoweringLegalizer &) = delete;
 
   public:
     explicit PostLoweringLegalizer(TargetARM32 *Target)
         : Target(Target), StackOrFrameReg(Target->getPhysicalRegister(
@@ skipping 246 matching lines @@
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H