Subzero. ARM32. Fixes bugs uncovered by the gcc torture tests.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2711 matching lines @@
     // ARM, shifts only take the lower 8 bits of the shift register, and
     // saturate to the range 0-32, so the negative value will saturate to 32.
     Operand *_32 = legalize(Ctx->getConstantInt32(32), Legal_Reg | Legal_Flex);
     Operand *_0 =
         legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
     Variable *T0 = makeReg(IceType_i32);
     Variable *T1 = makeReg(IceType_i32);
     Variable *T2 = makeReg(IceType_i32);
     Variable *TA_Hi = makeReg(IceType_i32);
     Variable *TA_Lo = makeReg(IceType_i32);
-    Variable *Src0RLo = SrcsLo.src0R(this);
+    Variable *Src0RLo = SrcsLo.unswappedSrc0R(this);
     Variable *Src0RHi = SrcsHi.unswappedSrc0R(this);
     Variable *Src1RLo = SrcsLo.unswappedSrc1R(this);
     _rsb(T0, Src1RLo, _32);
     _lsr(T1, Src0RLo, T0);
     _orr(TA_Hi, T1, OperandARM32FlexReg::create(Func, IceType_i32, Src0RHi,
                                                 OperandARM32::LSL, Src1RLo));
     _sub(T2, Src1RLo, _32);
     _cmp(T2, _0);
     _lsl(TA_Hi, Src0RLo, T2, CondARM32::GE);
     _set_dest_redefined();
@@ skipping 3738 matching lines @@
     // peephole style optimizations during or before lowering have access to
     // this instruction in undeleted form. See for example
     // tryOptimizedCmpxchgCmpBr().
     Iter->second.Instr->setDead();
     ++Iter;
   }
 }
 
 TargetARM32::Sandboxer::Sandboxer(TargetARM32 *Target,
                                   InstBundleLock::Option BundleOption)
-    : Bundler(Target, BundleOption), Target(Target) {}
+    : Target(Target), BundleOption(BundleOption) {}
 
 TargetARM32::Sandboxer::~Sandboxer() {}
 
 namespace {
 OperandARM32FlexImm *indirectBranchBicMask(Cfg *Func) {
   constexpr uint32_t Imm8 = 0xFC; // 0xC000000F
   constexpr uint32_t RotateAmt = 2;
   return OperandARM32FlexImm::create(Func, IceType_i32, Imm8, RotateAmt);
 }
 
 OperandARM32FlexImm *memOpBicMask(Cfg *Func) {
   constexpr uint32_t Imm8 = 0x0C; // 0xC0000000
   constexpr uint32_t RotateAmt = 2;
   return OperandARM32FlexImm::create(Func, IceType_i32, Imm8, RotateAmt);
 }
 
 static bool baseNeedsBic(Variable *Base) {
   return Base->getRegNum() != RegARM32::Reg_r9 &&
          Base->getRegNum() != RegARM32::Reg_sp;
 }
 } // end of anonymous namespace
 
+void TargetARM32::Sandboxer::createAutoBundle() {
+  Bundler = makeUnique<AutoBundle>(Target, BundleOption);
+}
+
 void TargetARM32::Sandboxer::add_sp(Operand *AddAmount) {
   Variable *SP = Target->getPhysicalRegister(RegARM32::Reg_sp);
+  if (!Target->NeedSandboxing) {
+    Target->_add(SP, SP, AddAmount);
+    return;
+  }
+  createAutoBundle();
   Target->_add(SP, SP, AddAmount);
-  if (Target->NeedSandboxing) {
-    Target->_bic(SP, SP, memOpBicMask(Target->Func));
-  }
+  Target->_bic(SP, SP, memOpBicMask(Target->Func));
 }
 
 void TargetARM32::Sandboxer::align_sp(size_t Alignment) {
   Variable *SP = Target->getPhysicalRegister(RegARM32::Reg_sp);
+  if (!Target->NeedSandboxing) {
+    Target->alignRegisterPow2(SP, Alignment);
+    return;
+  }
+  createAutoBundle();
   Target->alignRegisterPow2(SP, Alignment);
-  if (Target->NeedSandboxing) {
-    Target->_bic(SP, SP, memOpBicMask(Target->Func));
-  }
+  Target->_bic(SP, SP, memOpBicMask(Target->Func));
 }
 
 InstARM32Call *TargetARM32::Sandboxer::bl(Variable *ReturnReg,
                                           Operand *CallTarget) {
   if (Target->NeedSandboxing) {
+    createAutoBundle();
     if (auto *CallTargetR = llvm::dyn_cast<Variable>(CallTarget)) {
       Target->_bic(CallTargetR, CallTargetR,
                    indirectBranchBicMask(Target->Func));
     }
   }
   return Target->Context.insert<InstARM32Call>(ReturnReg, CallTarget);
 }
 
 void TargetARM32::Sandboxer::ldr(Variable *Dest, OperandARM32Mem *Mem,
                                  CondARM32::Cond Pred) {
   Variable *MemBase = Mem->getBase();
   if (Target->NeedSandboxing && baseNeedsBic(MemBase)) {
+    createAutoBundle();
     assert(!Mem->isRegReg());
     Target->_bic(MemBase, MemBase, memOpBicMask(Target->Func), Pred);
   }
   Target->_ldr(Dest, Mem, Pred);
 }
 
 void TargetARM32::Sandboxer::ldrex(Variable *Dest, OperandARM32Mem *Mem,
                                    CondARM32::Cond Pred) {
   Variable *MemBase = Mem->getBase();
   if (Target->NeedSandboxing && baseNeedsBic(MemBase)) {
+    createAutoBundle();
     assert(!Mem->isRegReg());
     Target->_bic(MemBase, MemBase, memOpBicMask(Target->Func), Pred);
   }
   Target->_ldrex(Dest, Mem, Pred);
 }
 
 void TargetARM32::Sandboxer::reset_sp(Variable *Src) {
   Variable *SP = Target->getPhysicalRegister(RegARM32::Reg_sp);
+  if (!Target->NeedSandboxing) {
+    Target->_mov_redefined(SP, Src);
+    return;
+  }
+  createAutoBundle();
   Target->_mov_redefined(SP, Src);
-  if (Target->NeedSandboxing) {
-    Target->_bic(SP, SP, memOpBicMask(Target->Func));
-  }
+  Target->_bic(SP, SP, memOpBicMask(Target->Func));
 }
 
 void TargetARM32::Sandboxer::ret(Variable *RetAddr, Variable *RetValue) {
   if (Target->NeedSandboxing) {
+    createAutoBundle();
     Target->_bic(RetAddr, RetAddr, indirectBranchBicMask(Target->Func));
   }
   Target->_ret(RetAddr, RetValue);
 }
 
 void TargetARM32::Sandboxer::str(Variable *Src, OperandARM32Mem *Mem,
                                  CondARM32::Cond Pred) {
   Variable *MemBase = Mem->getBase();
   if (Target->NeedSandboxing && baseNeedsBic(MemBase)) {
+    createAutoBundle();
     assert(!Mem->isRegReg());
     Target->_bic(MemBase, MemBase, memOpBicMask(Target->Func), Pred);
   }
   Target->_str(Src, Mem, Pred);
 }
 
 void TargetARM32::Sandboxer::strex(Variable *Dest, Variable *Src,
                                    OperandARM32Mem *Mem, CondARM32::Cond Pred) {
   Variable *MemBase = Mem->getBase();
   if (Target->NeedSandboxing && baseNeedsBic(MemBase)) {
+    createAutoBundle();
     assert(!Mem->isRegReg());
     Target->_bic(MemBase, MemBase, memOpBicMask(Target->Func), Pred);
   }
   Target->_strex(Dest, Src, Mem, Pred);
 }
 
 void TargetARM32::Sandboxer::sub_sp(Operand *SubAmount) {
   Variable *SP = Target->getPhysicalRegister(RegARM32::Reg_sp);
+  if (!Target->NeedSandboxing) {
+    Target->_sub(SP, SP, SubAmount);
+    return;
+  }
+  createAutoBundle();
   Target->_sub(SP, SP, SubAmount);
-  if (Target->NeedSandboxing) {
-    Target->_bic(SP, SP, memOpBicMask(Target->Func));
-  }
+  Target->_bic(SP, SP, memOpBicMask(Target->Func));
 }
 
 TargetDataARM32::TargetDataARM32(GlobalContext *Ctx)
     : TargetDataLowering(Ctx) {}
 
 void TargetDataARM32::lowerGlobals(const VariableDeclarationList &Vars,
                                    const IceString &SectionSuffix) {
   const bool IsPIC = Ctx->getFlags().getUseNonsfi();
   switch (Ctx->getFlags().getOutFileType()) {
   case FT_Elf: {
@@ skipping 184 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice