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Issue 1745393002: Subzero. ARM32. Reverts cl 1687553002. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 9 months ago
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1 ; Simple test of the select instruction. The CHECK lines are only 1 ; Simple test of the select instruction. The CHECK lines are only
2 ; checking for basic instruction patterns that should be present 2 ; checking for basic instruction patterns that should be present
3 ; regardless of the optimization level, so there are no special OPTM1 3 ; regardless of the optimization level, so there are no special OPTM1
4 ; match lines. 4 ; match lines.
5 5
6 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 6 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
7 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \ 7 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
8 ; RUN: | %if --need=target_X8632 --command FileCheck %s 8 ; RUN: | %if --need=target_X8632 --command FileCheck %s
9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \ 10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
44 ; CHECK-LABEL: testSelect 44 ; CHECK-LABEL: testSelect
45 ; CHECK: cmp 45 ; CHECK: cmp
46 ; CHECK: cmp 46 ; CHECK: cmp
47 ; CHECK: call {{.*}} R_{{.*}} useInt 47 ; CHECK: call {{.*}} R_{{.*}} useInt
48 ; CHECK: cmp 48 ; CHECK: cmp
49 ; CHECK: cmp 49 ; CHECK: cmp
50 ; CHECK: call {{.*}} R_{{.*}} useInt 50 ; CHECK: call {{.*}} R_{{.*}} useInt
51 ; CHECK: ret 51 ; CHECK: ret
52 ; ARM32-LABEL: testSelect 52 ; ARM32-LABEL: testSelect
53 ; ARM32: cmp 53 ; ARM32: cmp
54 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} useInt 54 ; ARM32: bl {{.*}} useInt
55 ; ARM32: movt [[CALL]]
56 ; ARM32; blx [[CALL]]
57 ; ARM32-Om1: mov {{.*}}, #20 55 ; ARM32-Om1: mov {{.*}}, #20
58 ; ARM32-O2: mov [[REG:r[0-9]+]], #20 56 ; ARM32-O2: mov [[REG:r[0-9]+]], #20
59 ; ARM32: tst 57 ; ARM32: tst
60 ; ARM32-Om1: movne {{.*}}, #10 58 ; ARM32-Om1: movne {{.*}}, #10
61 ; ARM32-O2: movne [[REG]], #10 59 ; ARM32-O2: movne [[REG]], #10
62 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} useInt 60 ; ARM32: bl {{.*}} useInt
63 ; ARM32: movt [[CALL]] 61 ; ARM32: bl {{.*}} useInt
64 ; ARM32; blx [[CALL]] 62 ; ARM32: bl {{.*}} useInt
65 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} useInt
66 ; ARM32: movt [[CALL]]
67 ; ARM32; blx [[CALL]]
68 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} useInt
69 ; ARM32: movt [[CALL]]
70 ; ARM32; blx [[CALL]]
71 ; ARM32: bx lr 63 ; ARM32: bx lr
72 64
73 ; Check for valid addressing mode in the cmp instruction when the 65 ; Check for valid addressing mode in the cmp instruction when the
74 ; operand is an immediate. 66 ; operand is an immediate.
75 define internal i32 @testSelectImm32(i32 %a, i32 %b) { 67 define internal i32 @testSelectImm32(i32 %a, i32 %b) {
76 entry: 68 entry:
77 %cond = select i1 false, i32 %a, i32 %b 69 %cond = select i1 false, i32 %a, i32 %b
78 ret i32 %cond 70 ret i32 %cond
79 } 71 }
80 ; CHECK-LABEL: testSelectImm32 72 ; CHECK-LABEL: testSelectImm32
81 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}}, 73 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
82 ; ARM32-LABEL: testSelectImm32 74 ; ARM32-LABEL: testSelectImm32
83 ; ARM32-NOT: cmp #{{.*}}, 75 ; ARM32-NOT: cmp #{{.*}},
84 76
85 ; Check for valid addressing mode in the cmp instruction when the 77 ; Check for valid addressing mode in the cmp instruction when the
86 ; operand is an immediate. There is a different x86-32 lowering 78 ; operand is an immediate. There is a different x86-32 lowering
87 ; sequence for 64-bit operands. 79 ; sequence for 64-bit operands.
88 define internal i64 @testSelectImm64(i64 %a, i64 %b) { 80 define internal i64 @testSelectImm64(i64 %a, i64 %b) {
89 entry: 81 entry:
90 %cond = select i1 true, i64 %a, i64 %b 82 %cond = select i1 true, i64 %a, i64 %b
91 ret i64 %cond 83 ret i64 %cond
92 } 84 }
93 ; CHECK-LABEL: testSelectImm64 85 ; CHECK-LABEL: testSelectImm64
94 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}}, 86 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
95 ; ARM32-LABEL: testSelectImm64 87 ; ARM32-LABEL: testSelectImm64
96 ; ARM32-NOT: cmp #{{.*}}, 88 ; ARM32-NOT: cmp #{{.*}},
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