Subzero. ARM32. Reverts cl 1687553002.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 3574 matching lines @@
   case CondARM32::kNone:
     _br(TargetFalse);
     break;
   case CondARM32::AL:
     _br(TargetTrue);
     break;
   }
 }
 
 void TargetARM32::lowerCall(const InstCall *Instr) {
-  // Note: Keep original call target. This allows us to call the correct
-  // postamble helper, even if the CallTarget gets modified during lowering.
-  Operand *OrigCallTarget = Instr->getCallTarget();
-  Operand *CallTarget = OrigCallTarget;
+  Operand *CallTarget = Instr->getCallTarget();
   if (Instr->isTargetHelperCall()) {
     auto TargetHelperPreamble = ARM32HelpersPreamble.find(CallTarget);
     if (TargetHelperPreamble != ARM32HelpersPreamble.end()) {
       (this->*TargetHelperPreamble->second)(Instr);
     }
   }
   MaybeLeafFunc = false;
   NeedsStackAlignment = true;
 
   // Assign arguments to registers and stack. Also reserve stack.
@@ skipping 104 matching lines @@
     case IceType_v16i1:
     case IceType_v16i8:
     case IceType_v8i16:
     case IceType_v4i32:
     case IceType_v4f32:
       ReturnReg = makeReg(Dest->getType(), RegARM32::Reg_q0);
       break;
     }
   }
 
-  // Note: To allow far calls, even for constant relocatables, we force
-  // the call target into a register, and make an indirect call.
-  CallTarget = legalizeToReg(CallTarget);
+  // Allow ConstantRelocatable to be left alone as a direct call, but force
+  // other constants like ConstantInteger32 to be in a register and make it an
+  // indirect call.
+  if (!llvm::isa<ConstantRelocatable>(CallTarget)) {
+    CallTarget = legalize(CallTarget, Legal_Reg);
+  }
 
   // Copy arguments to be passed in registers to the appropriate registers.
   CfgVector<Variable *> RegArgs;
   for (auto &FPArg : FPArgs) {
     RegArgs.emplace_back(legalizeToReg(FPArg.first, FPArg.second));
   }
   for (auto &GPRArg : GPRArgs) {
     RegArgs.emplace_back(legalizeToReg(GPRArg.first, GPRArg.second));
   }
 
@@ skipping 34 matching lines @@
         } else {
           assert(isIntegerType(Dest->getType()) &&
                  typeWidthInBytes(Dest->getType()) <= 4);
           _mov(Dest, ReturnReg);
         }
       }
     }
   }
 
   if (Instr->isTargetHelperCall()) {
-    auto TargetHelpersPostamble = ARM32HelpersPostamble.find(OrigCallTarget);
+    auto TargetHelpersPostamble = ARM32HelpersPostamble.find(CallTarget);
     if (TargetHelpersPostamble != ARM32HelpersPostamble.end()) {
       (this->*TargetHelpersPostamble->second)(Instr);
     }
   }
 }
 
 namespace {
 void configureBitcastTemporary(Variable64On32 *Var) {
   Var->setMustNotHaveReg();
   Var->getHi()->setMustHaveReg();
@@ skipping 3005 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice