Subzero. Performance tweaks.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 134 matching lines @@
   void dump(const Cfg *Func) const;
 
 private:
   /// Returns true if Producers contains a valid entry for the given VarNum.
   bool containsValid(SizeT VarNum) const {
     auto Element = Producers.find(VarNum);
     return Element != Producers.end() && Element->second.Instr != nullptr;
   }
   void setInvalid(SizeT VarNum) { Producers[VarNum].Instr = nullptr; }
   /// Producers maps Variable::Number to a BoolFoldingEntry.
-  std::unordered_map<SizeT, BoolFoldingEntry<Traits>> Producers;
+  CfgUnorderedMap<SizeT, BoolFoldingEntry<Traits>> Producers;
 };
 
 template <typename Traits>
 BoolFoldingEntry<Traits>::BoolFoldingEntry(Inst *I)
     : Instr(I), IsComplex(BoolFolding<Traits>::hasComplexLowering(I)) {}
 
 template <typename Traits>
 typename BoolFolding<Traits>::BoolFoldingProducerKind
 BoolFolding<Traits>::getProducerKind(const Inst *Instr) {
   if (llvm::isa<InstIcmp>(Instr)) {
@@ skipping 789 matching lines @@
   // registers (as a side effect, this gives variables a second chance at
   // physical register assignment).
   //
   // A middle ground approach is to leverage sparsity and allocate one block of
   // space on the frame for globals (variables with multi-block lifetime), and
   // one block to share for locals (single-block lifetime).
 
   Context.init(Node);
   Context.setInsertPoint(Context.getCur());
 
-  llvm::SmallBitVector CalleeSaves =
-      getRegisterSet(RegSet_CalleeSave, RegSet_None);
-  RegsUsed = llvm::SmallBitVector(CalleeSaves.size());
+  SmallBitVector CalleeSaves = getRegisterSet(RegSet_CalleeSave, RegSet_None);
+  RegsUsed = SmallBitVector(CalleeSaves.size());
   VarList SortedSpilledVariables, VariablesLinkedToSpillSlots;
   size_t GlobalsSize = 0;
   // If there is a separate locals area, this represents that area. Otherwise
   // it counts any variable not counted by GlobalsSize.
   SpillAreaSizeBytes = 0;
   // If there is a separate locals area, this specifies the alignment for it.
   uint32_t LocalsSlotsAlignmentBytes = 0;
   // The entire spill locations area gets aligned to largest natural alignment
   // of the variables that have a spill slot.
   uint32_t SpillAreaAlignmentBytes = 0;
@@ skipping 15 matching lines @@
   // Compute the list of spilled variables and bounds for GlobalsSize, etc.
   getVarStackSlotParams(SortedSpilledVariables, RegsUsed, &GlobalsSize,
                         &SpillAreaSizeBytes, &SpillAreaAlignmentBytes,
                         &LocalsSlotsAlignmentBytes, TargetVarHook);
   uint32_t LocalsSpillAreaSize = SpillAreaSizeBytes;
   SpillAreaSizeBytes += GlobalsSize;
 
   // Add push instructions for preserved registers.
   uint32_t NumCallee = 0;
   size_t PreservedRegsSizeBytes = 0;
-  llvm::SmallBitVector Pushed(CalleeSaves.size());
+  SmallBitVector Pushed(CalleeSaves.size());
   for (RegNumT i : RegNumBVIter(CalleeSaves)) {
     const auto Canonical = Traits::getBaseReg(i);
     assert(Canonical == Traits::getBaseReg(Canonical));
     if (RegsUsed[i]) {
       Pushed[Canonical] = true;
     }
   }
   for (RegNumT RegNum : RegNumBVIter(Pushed)) {
     assert(RegNum == Traits::getBaseReg(RegNum));
     ++NumCallee;
@@ skipping 235 matching lines @@
   if (IsEbpBasedFrame) {
     _unlink_bp();
   } else {
     // add stackptr, SpillAreaSizeBytes
     if (SpillAreaSizeBytes != 0) {
       _add_sp(Ctx->getConstantInt32(SpillAreaSizeBytes));
     }
   }
 
   // Add pop instructions for preserved registers.
-  llvm::SmallBitVector CalleeSaves =
-      getRegisterSet(RegSet_CalleeSave, RegSet_None);
-  llvm::SmallBitVector Popped(CalleeSaves.size());
+  SmallBitVector CalleeSaves = getRegisterSet(RegSet_CalleeSave, RegSet_None);
+  SmallBitVector Popped(CalleeSaves.size());
   for (int32_t i = CalleeSaves.size() - 1; i >= 0; --i) {
     const auto RegNum = RegNumT::fromInt(i);
     if (RegNum == getFrameReg() && IsEbpBasedFrame)
       continue;
     const RegNumT Canonical = Traits::getBaseReg(RegNum);
     if (CalleeSaves[i] && RegsUsed[i]) {
       Popped[Canonical] = true;
     }
   }
   for (int32_t i = Popped.size() - 1; i >= 0; --i) {
@@ skipping 82 matching lines @@
     // Test if the Offset is an eligible i32 constants for randomization and
     // pooling. Blind/pool it if it is. Otherwise return as oridinary mem
     // operand.
     return legalize(MemOperand);
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
 template <typename TraitsType>
-llvm::SmallBitVector
+SmallBitVector
 TargetX86Base<TraitsType>::getRegisterSet(RegSetMask Include,
                                           RegSetMask Exclude) const {
   return Traits::getRegisterSet(Ctx->getFlags(), Include, Exclude);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerAlloca(const InstAlloca *Instr) {
   // Conservatively require the stack to be aligned. Some stack adjustment
   // operations implemented below assume that the stack is aligned before the
   // alloca. All the alloca code ensures that the stack alignment is preserved
@@ skipping 2934 matching lines @@
   // I is currently the InstIntrinsicCall. Peek past that.
   // This assumes that the atomic cmpxchg has not been lowered yet,
   // so that the instructions seen in the scan from "Cur" is simple.
   assert(llvm::isa<InstIntrinsicCall>(*I));
   Inst *NextInst = Context.getNextInst(I);
   if (!NextInst)
     return false;
   // There might be phi assignments right before the compare+branch, since this
   // could be a backward branch for a loop. This placement of assignments is
   // determined by placePhiStores().
-  std::vector<InstAssign *> PhiAssigns;
+  CfgVector<InstAssign *> PhiAssigns;
   while (auto *PhiAssign = llvm::dyn_cast<InstAssign>(NextInst)) {
     if (PhiAssign->getDest() == Dest)
       return false;
     PhiAssigns.push_back(PhiAssign);
     NextInst = Context.getNextInst(I);
     if (!NextInst)
       return false;
   }
   if (auto *NextCmp = llvm::dyn_cast<InstIcmp>(NextInst)) {
     if (!(NextCmp->getCondition() == InstIcmp::Eq &&
@@ skipping 2044 matching lines @@
     InstCall *Call = makeHelperCall(HelperName, CallDest, MaxSrcs);
     Call->addArg(Src0);
     StackArgumentsSize = getCallStackArgumentsSizeBytes(Call);
     Context.insert(Call);
     // The PNaCl ABI disallows i8/i16 return types, so truncate the helper call
     // result to the appropriate type as necessary.
     if (CallDest->getType() != Dest->getType())
       Context.insert<InstCast>(InstCast::Trunc, Dest, CallDest);
     Cast->setDeleted();
   } else if (auto *Intrinsic = llvm::dyn_cast<InstIntrinsicCall>(Instr)) {
-    std::vector<Type> ArgTypes;
+    CfgVector<Type> ArgTypes;
     Type ReturnType = IceType_void;
     switch (Intrinsics::IntrinsicID ID = Intrinsic->getIntrinsicInfo().ID) {
     default:
       return;
     case Intrinsics::Ctpop: {
       Operand *Val = Intrinsic->getArg(0);
       Type ValTy = Val->getType();
       if (ValTy == IceType_i64)
         ArgTypes = {IceType_i64};
       else
@@ skipping 37 matching lines @@
     StackArgumentsSize = typeWidthInBytes(ReturnType);
   } else {
     return;
   }
   StackArgumentsSize = Traits::applyStackAlignment(StackArgumentsSize);
   updateMaxOutArgsSizeBytes(StackArgumentsSize);
 }
 
 template <typename TraitsType>
 uint32_t TargetX86Base<TraitsType>::getCallStackArgumentsSizeBytes(
-    const std::vector<Type> &ArgTypes, Type ReturnType) {
+    const CfgVector<Type> &ArgTypes, Type ReturnType) {
   uint32_t OutArgumentsSizeBytes = 0;
   uint32_t XmmArgCount = 0;
   uint32_t GprArgCount = 0;
   for (Type Ty : ArgTypes) {
     // The PNaCl ABI requires the width of arguments to be at least 32 bits.
     assert(typeWidthInBytes(Ty) >= 4);
     if (isVectorType(Ty) && XmmArgCount < Traits::X86_MAX_XMM_ARGS) {
       ++XmmArgCount;
     } else if (isScalarIntegerType(Ty) &&
                GprArgCount < Traits::X86_MAX_GPR_ARGS) {
@@ skipping 16 matching lines @@
         std::max(OutArgumentsSizeBytes,
                  static_cast<uint32_t>(typeWidthInBytesOnStack(ReturnType)));
   }
   return OutArgumentsSizeBytes;
 }
 
 template <typename TraitsType>
 uint32_t TargetX86Base<TraitsType>::getCallStackArgumentsSizeBytes(
     const InstCall *Instr) {
   // Build a vector of the arguments' types.
-  std::vector<Type> ArgTypes;
-  for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
+  const SizeT NumArgs = Instr->getNumArgs();
+  CfgVector<Type> ArgTypes;
+  ArgTypes.reserve(NumArgs);
+  for (SizeT i = 0; i < NumArgs; ++i) {
     Operand *Arg = Instr->getArg(i);
     ArgTypes.emplace_back(Arg->getType());
   }
   // Compute the return type (if any);
   Type ReturnType = IceType_void;
   Variable *Dest = Instr->getDest();
   if (Dest != nullptr)
     ReturnType = Dest->getType();
   return getCallStackArgumentsSizeBytes(ArgTypes, ReturnType);
 }
@@ skipping 497 matching lines @@
 template <typename TraitsType> void TargetX86Base<TraitsType>::postLower() {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
   markRedefinitions();
   Context.availabilityUpdate();
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<RegNumT> &Permutation,
-    const llvm::SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
+    const SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   Traits::makeRandomRegisterPermutation(Ctx, Func, Permutation,
                                         ExcludeRegisters, Salt);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::emit(const ConstantInteger32 *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   Str << "$" << C->getValue();
@@ skipping 394 matching lines @@
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H