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1 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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474 template <typename T> struct length<T> { | 474 template <typename T> struct length<T> { |
475 static constexpr std::size_t value = 1; | 475 static constexpr std::size_t value = 1; |
476 }; | 476 }; |
477 | 477 |
478 const std::size_t Size; | 478 const std::size_t Size; |
479 }; | 479 }; |
480 | 480 |
481 public: | 481 public: |
482 static void initRegisterSet( | 482 static void initRegisterSet( |
483 const ::Ice::ClFlags &Flags, | 483 const ::Ice::ClFlags &Flags, |
484 std::array<llvm::SmallBitVector, RCX86_NUM> *TypeToRegisterSet, | 484 std::array<SmallBitVector, RCX86_NUM> *TypeToRegisterSet, |
485 std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases) { | 485 std::array<SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases) { |
486 llvm::SmallBitVector IntegerRegistersI64(RegisterSet::Reg_NUM); | 486 SmallBitVector IntegerRegistersI64(RegisterSet::Reg_NUM); |
487 llvm::SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM); | 487 SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM); |
488 llvm::SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM); | 488 SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM); |
489 llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM); | 489 SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM); |
490 llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM); | 490 SmallBitVector FloatRegisters(RegisterSet::Reg_NUM); |
491 llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM); | 491 SmallBitVector VectorRegisters(RegisterSet::Reg_NUM); |
492 llvm::SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM); | 492 SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM); |
493 llvm::SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM); | 493 SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM); |
494 llvm::SmallBitVector Trunc16To8Registers(RegisterSet::Reg_NUM); | 494 SmallBitVector Trunc16To8Registers(RegisterSet::Reg_NUM); |
495 llvm::SmallBitVector Trunc8RcvrRegisters(RegisterSet::Reg_NUM); | 495 SmallBitVector Trunc8RcvrRegisters(RegisterSet::Reg_NUM); |
496 llvm::SmallBitVector AhRcvrRegisters(RegisterSet::Reg_NUM); | 496 SmallBitVector AhRcvrRegisters(RegisterSet::Reg_NUM); |
497 llvm::SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM); | 497 SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM); |
498 | 498 |
499 static constexpr struct { | 499 static constexpr struct { |
500 uint16_t Val; | 500 uint16_t Val; |
501 unsigned IsReservedWhenSandboxing : 1; | 501 unsigned IsReservedWhenSandboxing : 1; |
502 unsigned Is64 : 1; | 502 unsigned Is64 : 1; |
503 unsigned Is32 : 1; | 503 unsigned Is32 : 1; |
504 unsigned Is16 : 1; | 504 unsigned Is16 : 1; |
505 unsigned Is8 : 1; | 505 unsigned Is8 : 1; |
506 unsigned IsXmm : 1; | 506 unsigned IsXmm : 1; |
507 unsigned Is64To8 : 1; | 507 unsigned Is64To8 : 1; |
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573 (*TypeToRegisterSet)[RC_v8i16] = VectorRegisters; | 573 (*TypeToRegisterSet)[RC_v8i16] = VectorRegisters; |
574 (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters; | 574 (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters; |
575 (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters; | 575 (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters; |
576 (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers; | 576 (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers; |
577 (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers; | 577 (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers; |
578 (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers; | 578 (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers; |
579 (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters; | 579 (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters; |
580 (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters; | 580 (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters; |
581 } | 581 } |
582 | 582 |
583 static llvm::SmallBitVector | 583 static SmallBitVector getRegisterSet(const ::Ice::ClFlags &Flags, |
584 getRegisterSet(const ::Ice::ClFlags &Flags, | 584 TargetLowering::RegSetMask Include, |
585 TargetLowering::RegSetMask Include, | 585 TargetLowering::RegSetMask Exclude) { |
586 TargetLowering::RegSetMask Exclude) { | 586 SmallBitVector Registers(RegisterSet::Reg_NUM); |
587 llvm::SmallBitVector Registers(RegisterSet::Reg_NUM); | |
588 | 587 |
589 const bool NeedSandboxing = Flags.getUseSandboxing(); | 588 const bool NeedSandboxing = Flags.getUseSandboxing(); |
590 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ | 589 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
591 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ | 590 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ |
592 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ | 591 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ |
593 if (!NeedSandboxing || !(sboxres)) { \ | 592 if (!NeedSandboxing || !(sboxres)) { \ |
594 if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave)) \ | 593 if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave)) \ |
595 Registers[RegisterSet::val] = true; \ | 594 Registers[RegisterSet::val] = true; \ |
596 if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave)) \ | 595 if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave)) \ |
597 Registers[RegisterSet::val] = true; \ | 596 Registers[RegisterSet::val] = true; \ |
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612 REGX8664_TABLE | 611 REGX8664_TABLE |
613 | 612 |
614 #undef X | 613 #undef X |
615 | 614 |
616 return Registers; | 615 return Registers; |
617 } | 616 } |
618 | 617 |
619 static void | 618 static void |
620 makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func, | 619 makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func, |
621 llvm::SmallVectorImpl<RegNumT> &Permutation, | 620 llvm::SmallVectorImpl<RegNumT> &Permutation, |
622 const llvm::SmallBitVector &ExcludeRegisters, | 621 const SmallBitVector &ExcludeRegisters, |
623 uint64_t Salt) { | 622 uint64_t Salt) { |
624 // TODO(stichnot): Declaring Permutation this way loses type/size | 623 // TODO(stichnot): Declaring Permutation this way loses type/size |
625 // information. Fix this in conjunction with the caller-side TODO. | 624 // information. Fix this in conjunction with the caller-side TODO. |
626 assert(Permutation.size() >= RegisterSet::Reg_NUM); | 625 assert(Permutation.size() >= RegisterSet::Reg_NUM); |
627 // Expected upper bound on the number of registers in a single equivalence | 626 // Expected upper bound on the number of registers in a single equivalence |
628 // class. For x86-64, this would comprise the 16 XMM registers. This is | 627 // class. For x86-64, this would comprise the 16 XMM registers. This is |
629 // for performance, not correctness. | 628 // for performance, not correctness. |
630 static const unsigned MaxEquivalenceClassSize = 8; | 629 static const unsigned MaxEquivalenceClassSize = 8; |
631 using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>; | 630 using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>; |
632 using EquivalenceClassMap = std::map<uint32_t, RegisterList>; | 631 using EquivalenceClassMap = std::map<uint32_t, RegisterList>; |
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1032 const char *FldString; // s, l, or <blank> | 1031 const char *FldString; // s, l, or <blank> |
1033 } TypeAttributes[]; | 1032 } TypeAttributes[]; |
1034 }; | 1033 }; |
1035 | 1034 |
1036 using Traits = ::Ice::X8664::TargetX8664Traits; | 1035 using Traits = ::Ice::X8664::TargetX8664Traits; |
1037 } // end of namespace X8664 | 1036 } // end of namespace X8664 |
1038 | 1037 |
1039 } // end of namespace Ice | 1038 } // end of namespace Ice |
1040 | 1039 |
1041 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H | 1040 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H |
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