Subzero. Performance tweaks.

src/IceTargetLoweringX8664Traits.h

 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 463 matching lines @@
     template <typename T> struct length<T> {
       static constexpr std::size_t value = 1;
     };
 
     const std::size_t Size;
   };
 
 public:
   static void initRegisterSet(
       const ::Ice::ClFlags &Flags,
-      std::array<llvm::SmallBitVector, RCX86_NUM> *TypeToRegisterSet,
-      std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases) {
-    llvm::SmallBitVector IntegerRegistersI64(RegisterSet::Reg_NUM);
-    llvm::SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM);
-    llvm::SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM);
-    llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM);
-    llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM);
-    llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM);
-    llvm::SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM);
-    llvm::SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM);
-    llvm::SmallBitVector Trunc16To8Registers(RegisterSet::Reg_NUM);
-    llvm::SmallBitVector Trunc8RcvrRegisters(RegisterSet::Reg_NUM);
-    llvm::SmallBitVector AhRcvrRegisters(RegisterSet::Reg_NUM);
-    llvm::SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM);
+      std::array<SmallBitVector, RCX86_NUM> *TypeToRegisterSet,
+      std::array<SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases) {
+    SmallBitVector IntegerRegistersI64(RegisterSet::Reg_NUM);
+    SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM);
+    SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM);
+    SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM);
+    SmallBitVector FloatRegisters(RegisterSet::Reg_NUM);
+    SmallBitVector VectorRegisters(RegisterSet::Reg_NUM);
+    SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM);
+    SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM);
+    SmallBitVector Trunc16To8Registers(RegisterSet::Reg_NUM);
+    SmallBitVector Trunc8RcvrRegisters(RegisterSet::Reg_NUM);
+    SmallBitVector AhRcvrRegisters(RegisterSet::Reg_NUM);
+    SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM);
 
     static constexpr struct {
       uint16_t Val;
       unsigned IsReservedWhenSandboxing : 1;
       unsigned Is64 : 1;
       unsigned Is32 : 1;
       unsigned Is16 : 1;
       unsigned Is8 : 1;
       unsigned IsXmm : 1;
       unsigned Is64To8 : 1;
@@ skipping 65 matching lines @@
     (*TypeToRegisterSet)[RC_v8i16] = VectorRegisters;
     (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters;
     (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters;
     (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers;
     (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers;
     (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers;
     (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters;
     (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters;
   }
 
-  static llvm::SmallBitVector
-  getRegisterSet(const ::Ice::ClFlags &Flags,
-                 TargetLowering::RegSetMask Include,
-                 TargetLowering::RegSetMask Exclude) {
-    llvm::SmallBitVector Registers(RegisterSet::Reg_NUM);
+  static SmallBitVector getRegisterSet(const ::Ice::ClFlags &Flags,
+                                       TargetLowering::RegSetMask Include,
+                                       TargetLowering::RegSetMask Exclude) {
+    SmallBitVector Registers(RegisterSet::Reg_NUM);
 
     const bool NeedSandboxing = Flags.getUseSandboxing();
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
           sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,      \
           is16To8, isTrunc8Rcvr, isAhRcvr, aliases)                            \
   if (!NeedSandboxing || !(sboxres)) {                                         \
     if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave))       \
       Registers[RegisterSet::val] = true;                                      \
     if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave))     \
       Registers[RegisterSet::val] = true;                                      \
@@ skipping 14 matching lines @@
     REGX8664_TABLE
 
 #undef X
 
     return Registers;
   }
 
   static void
   makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func,
                                 llvm::SmallVectorImpl<RegNumT> &Permutation,
-                                const llvm::SmallBitVector &ExcludeRegisters,
+                                const SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) {
     // TODO(stichnot): Declaring Permutation this way loses type/size
     // information. Fix this in conjunction with the caller-side TODO.
     assert(Permutation.size() >= RegisterSet::Reg_NUM);
     // Expected upper bound on the number of registers in a single equivalence
     // class.  For x86-64, this would comprise the 16 XMM registers. This is
     // for performance, not correctness.
     static const unsigned MaxEquivalenceClassSize = 8;
     using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>;
     using EquivalenceClassMap = std::map<uint32_t, RegisterList>;
@@ skipping 399 matching lines @@
     const char *FldString;   // s, l, or <blank>
   } TypeAttributes[];
 };
 
 using Traits = ::Ice::X8664::TargetX8664Traits;
 } // end of namespace X8664
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H