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1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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446 template <typename T> struct __length<T> { | 446 template <typename T> struct __length<T> { |
447 static constexpr std::size_t value = 1; | 447 static constexpr std::size_t value = 1; |
448 }; | 448 }; |
449 | 449 |
450 const std::size_t Size; | 450 const std::size_t Size; |
451 }; | 451 }; |
452 | 452 |
453 public: | 453 public: |
454 static void initRegisterSet( | 454 static void initRegisterSet( |
455 const ::Ice::ClFlags & /*Flags*/, | 455 const ::Ice::ClFlags & /*Flags*/, |
456 std::array<llvm::SmallBitVector, RCX86_NUM> *TypeToRegisterSet, | 456 std::array<SmallBitVector, RCX86_NUM> *TypeToRegisterSet, |
457 std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases) { | 457 std::array<SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases) { |
458 llvm::SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM); | 458 SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM); |
459 llvm::SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM); | 459 SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM); |
460 llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM); | 460 SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM); |
461 llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM); | 461 SmallBitVector FloatRegisters(RegisterSet::Reg_NUM); |
462 llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM); | 462 SmallBitVector VectorRegisters(RegisterSet::Reg_NUM); |
463 llvm::SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM); | 463 SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM); |
464 llvm::SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM); | 464 SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM); |
465 llvm::SmallBitVector Trunc16To8Registers(RegisterSet::Reg_NUM); | 465 SmallBitVector Trunc16To8Registers(RegisterSet::Reg_NUM); |
466 llvm::SmallBitVector Trunc8RcvrRegisters(RegisterSet::Reg_NUM); | 466 SmallBitVector Trunc8RcvrRegisters(RegisterSet::Reg_NUM); |
467 llvm::SmallBitVector AhRcvrRegisters(RegisterSet::Reg_NUM); | 467 SmallBitVector AhRcvrRegisters(RegisterSet::Reg_NUM); |
468 llvm::SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM); | 468 SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM); |
469 | 469 |
470 static constexpr struct { | 470 static constexpr struct { |
471 uint16_t Val; | 471 uint16_t Val; |
472 unsigned Is64 : 1; | 472 unsigned Is64 : 1; |
473 unsigned Is32 : 1; | 473 unsigned Is32 : 1; |
474 unsigned Is16 : 1; | 474 unsigned Is16 : 1; |
475 unsigned Is8 : 1; | 475 unsigned Is8 : 1; |
476 unsigned IsXmm : 1; | 476 unsigned IsXmm : 1; |
477 unsigned Is64To8 : 1; | 477 unsigned Is64To8 : 1; |
478 unsigned Is32To8 : 1; | 478 unsigned Is32To8 : 1; |
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532 (*TypeToRegisterSet)[RC_v8i16] = VectorRegisters; | 532 (*TypeToRegisterSet)[RC_v8i16] = VectorRegisters; |
533 (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters; | 533 (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters; |
534 (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters; | 534 (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters; |
535 (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers; | 535 (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers; |
536 (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers; | 536 (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers; |
537 (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers; | 537 (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers; |
538 (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters; | 538 (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters; |
539 (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters; | 539 (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters; |
540 } | 540 } |
541 | 541 |
542 static llvm::SmallBitVector | 542 static SmallBitVector getRegisterSet(const ::Ice::ClFlags & /*Flags*/, |
543 getRegisterSet(const ::Ice::ClFlags & /*Flags*/, | 543 TargetLowering::RegSetMask Include, |
544 TargetLowering::RegSetMask Include, | 544 TargetLowering::RegSetMask Exclude) { |
545 TargetLowering::RegSetMask Exclude) { | 545 SmallBitVector Registers(RegisterSet::Reg_NUM); |
546 llvm::SmallBitVector Registers(RegisterSet::Reg_NUM); | |
547 | 546 |
548 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ | 547 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
549 isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, \ | 548 isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, \ |
550 isTrunc8Rcvr, isAhRcvr, aliases) \ | 549 isTrunc8Rcvr, isAhRcvr, aliases) \ |
551 if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave)) \ | 550 if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave)) \ |
552 Registers[RegisterSet::val] = true; \ | 551 Registers[RegisterSet::val] = true; \ |
553 if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave)) \ | 552 if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave)) \ |
554 Registers[RegisterSet::val] = true; \ | 553 Registers[RegisterSet::val] = true; \ |
555 if (stackptr && (Include & ::Ice::TargetLowering::RegSet_StackPointer)) \ | 554 if (stackptr && (Include & ::Ice::TargetLowering::RegSet_StackPointer)) \ |
556 Registers[RegisterSet::val] = true; \ | 555 Registers[RegisterSet::val] = true; \ |
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568 REGX8632_TABLE | 567 REGX8632_TABLE |
569 | 568 |
570 #undef X | 569 #undef X |
571 | 570 |
572 return Registers; | 571 return Registers; |
573 } | 572 } |
574 | 573 |
575 static void | 574 static void |
576 makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func, | 575 makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func, |
577 llvm::SmallVectorImpl<RegNumT> &Permutation, | 576 llvm::SmallVectorImpl<RegNumT> &Permutation, |
578 const llvm::SmallBitVector &ExcludeRegisters, | 577 const SmallBitVector &ExcludeRegisters, |
579 uint64_t Salt) { | 578 uint64_t Salt) { |
580 // TODO(stichnot): Declaring Permutation this way loses type/size | 579 // TODO(stichnot): Declaring Permutation this way loses type/size |
581 // information. Fix this in conjunction with the caller-side TODO. | 580 // information. Fix this in conjunction with the caller-side TODO. |
582 assert(Permutation.size() >= RegisterSet::Reg_NUM); | 581 assert(Permutation.size() >= RegisterSet::Reg_NUM); |
583 // Expected upper bound on the number of registers in a single equivalence | 582 // Expected upper bound on the number of registers in a single equivalence |
584 // class. For x86-32, this would comprise the 8 XMM registers. This is for | 583 // class. For x86-32, this would comprise the 8 XMM registers. This is for |
585 // performance, not correctness. | 584 // performance, not correctness. |
586 static const unsigned MaxEquivalenceClassSize = 8; | 585 static const unsigned MaxEquivalenceClassSize = 8; |
587 using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>; | 586 using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>; |
588 using EquivalenceClassMap = std::map<uint32_t, RegisterList>; | 587 using EquivalenceClassMap = std::map<uint32_t, RegisterList>; |
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991 | 990 |
992 static uint8_t InstSegmentPrefixes[]; | 991 static uint8_t InstSegmentPrefixes[]; |
993 }; | 992 }; |
994 | 993 |
995 using Traits = ::Ice::X8632::TargetX8632Traits; | 994 using Traits = ::Ice::X8632::TargetX8632Traits; |
996 } // end of namespace X8632 | 995 } // end of namespace X8632 |
997 | 996 |
998 } // end of namespace Ice | 997 } // end of namespace Ice |
999 | 998 |
1000 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H | 999 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H |
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