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1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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71 } | 71 } |
72 } | 72 } |
73 | 73 |
74 } // end of anonymous namespace | 74 } // end of anonymous namespace |
75 | 75 |
76 TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {} | 76 TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {} |
77 | 77 |
78 void TargetMIPS32::staticInit(GlobalContext *Ctx) { | 78 void TargetMIPS32::staticInit(GlobalContext *Ctx) { |
79 (void)Ctx; | 79 (void)Ctx; |
80 RegNumT::setLimit(RegMIPS32::Reg_NUM); | 80 RegNumT::setLimit(RegMIPS32::Reg_NUM); |
81 llvm::SmallBitVector IntegerRegisters(RegMIPS32::Reg_NUM); | 81 SmallBitVector IntegerRegisters(RegMIPS32::Reg_NUM); |
82 llvm::SmallBitVector I64PairRegisters(RegMIPS32::Reg_NUM); | 82 SmallBitVector I64PairRegisters(RegMIPS32::Reg_NUM); |
83 llvm::SmallBitVector Float32Registers(RegMIPS32::Reg_NUM); | 83 SmallBitVector Float32Registers(RegMIPS32::Reg_NUM); |
84 llvm::SmallBitVector Float64Registers(RegMIPS32::Reg_NUM); | 84 SmallBitVector Float64Registers(RegMIPS32::Reg_NUM); |
85 llvm::SmallBitVector VectorRegisters(RegMIPS32::Reg_NUM); | 85 SmallBitVector VectorRegisters(RegMIPS32::Reg_NUM); |
86 llvm::SmallBitVector InvalidRegisters(RegMIPS32::Reg_NUM); | 86 SmallBitVector InvalidRegisters(RegMIPS32::Reg_NUM); |
87 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 87 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
88 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 88 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
89 IntegerRegisters[RegMIPS32::val] = isInt; \ | 89 IntegerRegisters[RegMIPS32::val] = isInt; \ |
90 I64PairRegisters[RegMIPS32::val] = isI64Pair; \ | 90 I64PairRegisters[RegMIPS32::val] = isI64Pair; \ |
91 Float32Registers[RegMIPS32::val] = isFP32; \ | 91 Float32Registers[RegMIPS32::val] = isFP32; \ |
92 Float64Registers[RegMIPS32::val] = isFP64; \ | 92 Float64Registers[RegMIPS32::val] = isFP64; \ |
93 VectorRegisters[RegMIPS32::val] = isVec128; \ | 93 VectorRegisters[RegMIPS32::val] = isVec128; \ |
94 RegisterAliases[RegMIPS32::val].resize(RegMIPS32::Reg_NUM); \ | 94 RegisterAliases[RegMIPS32::val].resize(RegMIPS32::Reg_NUM); \ |
95 for (SizeT RegAlias : alias_init) { \ | 95 for (SizeT RegAlias : alias_init) { \ |
96 assert(!RegisterAliases[RegMIPS32::val][RegAlias] && \ | 96 assert(!RegisterAliases[RegMIPS32::val][RegAlias] && \ |
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524 Offset = | 524 Offset = |
525 llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(NextOffsetVal)); | 525 llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(NextOffsetVal)); |
526 } | 526 } |
527 return OperandMIPS32Mem::create(Func, SplitType, Base, Offset, | 527 return OperandMIPS32Mem::create(Func, SplitType, Base, Offset, |
528 Mem->getAddrMode()); | 528 Mem->getAddrMode()); |
529 } | 529 } |
530 llvm_unreachable("Unsupported operand type"); | 530 llvm_unreachable("Unsupported operand type"); |
531 return nullptr; | 531 return nullptr; |
532 } | 532 } |
533 | 533 |
534 llvm::SmallBitVector TargetMIPS32::getRegisterSet(RegSetMask Include, | 534 SmallBitVector TargetMIPS32::getRegisterSet(RegSetMask Include, |
535 RegSetMask Exclude) const { | 535 RegSetMask Exclude) const { |
536 llvm::SmallBitVector Registers(RegMIPS32::Reg_NUM); | 536 SmallBitVector Registers(RegMIPS32::Reg_NUM); |
537 | 537 |
538 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 538 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
539 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 539 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
540 if (scratch && (Include & RegSet_CallerSave)) \ | 540 if (scratch && (Include & RegSet_CallerSave)) \ |
541 Registers[RegMIPS32::val] = true; \ | 541 Registers[RegMIPS32::val] = true; \ |
542 if (preserved && (Include & RegSet_CalleeSave)) \ | 542 if (preserved && (Include & RegSet_CalleeSave)) \ |
543 Registers[RegMIPS32::val] = true; \ | 543 Registers[RegMIPS32::val] = true; \ |
544 if (stackptr && (Include & RegSet_StackPointer)) \ | 544 if (stackptr && (Include & RegSet_StackPointer)) \ |
545 Registers[RegMIPS32::val] = true; \ | 545 Registers[RegMIPS32::val] = true; \ |
546 if (frameptr && (Include & RegSet_FramePointer)) \ | 546 if (frameptr && (Include & RegSet_FramePointer)) \ |
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1143 void TargetMIPS32::postLower() { | 1143 void TargetMIPS32::postLower() { |
1144 if (Ctx->getFlags().getOptLevel() == Opt_m1) | 1144 if (Ctx->getFlags().getOptLevel() == Opt_m1) |
1145 return; | 1145 return; |
1146 // TODO(rkotler): Find two-address non-SSA instructions where Dest==Src0, | 1146 // TODO(rkotler): Find two-address non-SSA instructions where Dest==Src0, |
1147 // and set the IsDestRedefined flag to keep liveness analysis consistent. | 1147 // and set the IsDestRedefined flag to keep liveness analysis consistent. |
1148 UnimplementedError(Func->getContext()->getFlags()); | 1148 UnimplementedError(Func->getContext()->getFlags()); |
1149 } | 1149 } |
1150 | 1150 |
1151 void TargetMIPS32::makeRandomRegisterPermutation( | 1151 void TargetMIPS32::makeRandomRegisterPermutation( |
1152 llvm::SmallVectorImpl<RegNumT> &Permutation, | 1152 llvm::SmallVectorImpl<RegNumT> &Permutation, |
1153 const llvm::SmallBitVector &ExcludeRegisters, uint64_t Salt) const { | 1153 const SmallBitVector &ExcludeRegisters, uint64_t Salt) const { |
1154 (void)Permutation; | 1154 (void)Permutation; |
1155 (void)ExcludeRegisters; | 1155 (void)ExcludeRegisters; |
1156 (void)Salt; | 1156 (void)Salt; |
1157 UnimplementedError(Func->getContext()->getFlags()); | 1157 UnimplementedError(Func->getContext()->getFlags()); |
1158 } | 1158 } |
1159 | 1159 |
1160 /* TODO(jvoung): avoid duplicate symbols with multiple targets. | 1160 /* TODO(jvoung): avoid duplicate symbols with multiple targets. |
1161 void ConstantUndef::emitWithoutDollar(GlobalContext *) const { | 1161 void ConstantUndef::emitWithoutDollar(GlobalContext *) const { |
1162 llvm_unreachable("Not expecting to emitWithoutDollar undef"); | 1162 llvm_unreachable("Not expecting to emitWithoutDollar undef"); |
1163 } | 1163 } |
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1286 | 1286 |
1287 void TargetHeaderMIPS32::lower() { | 1287 void TargetHeaderMIPS32::lower() { |
1288 OstreamLocker L(Ctx); | 1288 OstreamLocker L(Ctx); |
1289 Ostream &Str = Ctx->getStrEmit(); | 1289 Ostream &Str = Ctx->getStrEmit(); |
1290 Str << "\t.set\t" | 1290 Str << "\t.set\t" |
1291 << "nomicromips\n"; | 1291 << "nomicromips\n"; |
1292 Str << "\t.set\t" | 1292 Str << "\t.set\t" |
1293 << "nomips16\n"; | 1293 << "nomips16\n"; |
1294 } | 1294 } |
1295 | 1295 |
1296 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; | 1296 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; |
1297 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; | 1297 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
1298 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 1298 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
1299 | 1299 |
1300 } // end of namespace MIPS32 | 1300 } // end of namespace MIPS32 |
1301 } // end of namespace Ice | 1301 } // end of namespace Ice |
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