Subzero. Performance tweaks.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Declares the TargetLoweringARM32 class, which implements the
 /// TargetLowering interface for the ARM 32-bit architecture.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICETARGETLOWERINGARM32_H
 #define SUBZERO_SRC_ICETARGETLOWERINGARM32_H
 
 #include "IceAssemblerARM32.h"
 #include "IceDefs.h"
 #include "IceInstARM32.h"
 #include "IceRegistersARM32.h"
 #include "IceTargetLowering.h"
 
-#include "llvm/ADT/SmallBitVector.h"
-
-#include <unordered_set>
-
 namespace Ice {
 namespace ARM32 {
 
 // Class encapsulating ARM cpu features / instruction set.
 class TargetARM32Features {
   TargetARM32Features() = delete;
   TargetARM32Features(const TargetARM32Features &) = delete;
   TargetARM32Features &operator=(const TargetARM32Features &) = delete;
 
 public:
@@ skipping 38 matching lines @@
   }
 
   void translateOm1() override;
   void translateO2() override;
   bool doBranchOpt(Inst *I, const CfgNode *NextNode) override;
 
   SizeT getNumRegisters() const override { return RegARM32::Reg_NUM; }
   Variable *getPhysicalRegister(RegNumT RegNum,
                                 Type Ty = IceType_void) override;
   IceString getRegName(RegNumT RegNum, Type Ty) const override;
-  llvm::SmallBitVector getRegisterSet(RegSetMask Include,
-                                      RegSetMask Exclude) const override;
-  const llvm::SmallBitVector &
+  SmallBitVector getRegisterSet(RegSetMask Include,
+                                RegSetMask Exclude) const override;
+  const SmallBitVector &
   getRegistersForVariable(const Variable *Var) const override {
     RegClass RC = Var->getRegClass();
     switch (RC) {
     default:
       assert(RC < RC_Target);
       return TypeToRegisterSet[RC];
     case RegARM32::RCARM32_QtoS:
       return TypeToRegisterSet[RC];
     }
   }
-  const llvm::SmallBitVector &
+  const SmallBitVector &
   getAllRegistersForVariable(const Variable *Var) const override {
     RegClass RC = Var->getRegClass();
     assert((RegARM32::RegClassARM32)RC < RegARM32::RCARM32_NUM);
     return TypeToRegisterSetUnfiltered[RC];
   }
-  const llvm::SmallBitVector &
-  getAliasesForRegister(RegNumT Reg) const override {
+  const SmallBitVector &getAliasesForRegister(RegNumT Reg) const override {
     return RegisterAliases[Reg];
   }
   bool hasFramePointer() const override { return UsesFramePointer; }
   void setHasFramePointer() override { UsesFramePointer = true; }
   RegNumT getStackReg() const override { return RegARM32::Reg_sp; }
   RegNumT getFrameReg() const override { return RegARM32::Reg_fp; }
   RegNumT getFrameOrStackReg() const override {
     return UsesFramePointer ? getFrameReg() : getStackReg();
   }
   RegNumT getReservedTmpReg() const { return RegARM32::Reg_ip; }
@@ skipping 177 matching lines @@
   static Type stackSlotType();
   Variable *copyToReg(Operand *Src, RegNumT RegNum = RegNumT());
   void alignRegisterPow2(Variable *Reg, uint32_t Align,
                          RegNumT TmpRegNum = RegNumT());
 
   /// Returns a vector in a register with the given constant entries.
   Variable *makeVectorOfZeros(Type Ty, RegNumT RegNum = RegNumT());
 
   void
   makeRandomRegisterPermutation(llvm::SmallVectorImpl<RegNumT> &Permutation,
-                                const llvm::SmallBitVector &ExcludeRegisters,
+                                const SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) const override;
 
   // If a divide-by-zero check is needed, inserts a: test; branch .LSKIP; trap;
   // .LSKIP: <continuation>. If no check is needed nothing is inserted.
   void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
   using ExtInstr = void (TargetARM32::*)(Variable *, Variable *,
                                          CondARM32::Cond);
   using DivInstr = void (TargetARM32::*)(Variable *, Variable *, Variable *,
                                          CondARM32::Cond);
   void lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R, Operand *Src1,
@@ skipping 575 matching lines @@
   // TODO(jpp): use CfgLocalAllocator.
   /// @}
 
   /// Manages the Gotoff relocations created during the function lowering. A
   /// single Gotoff relocation is created for each global variable used by the
   /// function being lowered.
   /// @{
   // TODO(jpp): if the same global G is used in different functions, then this
   // method will emit one G(gotoff) relocation per function.
   IceString createGotoffRelocation(const ConstantRelocatable *CR);
-  std::unordered_set<IceString> KnownGotoffs;
+  CfgUnorderedSet<IceString> KnownGotoffs;
   /// @}
 
   /// Loads the constant relocatable Name to Register. Then invoke Finish to
   /// finish the relocatable lowering. Finish **must** use PC in its first
   /// emitted instruction, or the relocatable in Register will contain the wrong
   /// value.
   //
   // Lowered sequence:
   //
   // Movw:
@@ skipping 197 matching lines @@
   TargetARM32Features CPUFeatures;
   bool UsesFramePointer = false;
   bool NeedsStackAlignment = false;
   bool MaybeLeafFunc = true;
   size_t SpillAreaSizeBytes = 0;
   size_t FixedAllocaSizeBytes = 0;
   size_t FixedAllocaAlignBytes = 0;
   bool PrologEmitsFixedAllocas = false;
   uint32_t MaxOutArgsSizeBytes = 0;
   // TODO(jpp): std::array instead of array.
-  static llvm::SmallBitVector TypeToRegisterSet[RegARM32::RCARM32_NUM];
-  static llvm::SmallBitVector
-      TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
-  static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM];
-  llvm::SmallBitVector RegsUsed;
+  static SmallBitVector TypeToRegisterSet[RegARM32::RCARM32_NUM];
+  static SmallBitVector TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
+  static SmallBitVector RegisterAliases[RegARM32::Reg_NUM];
+  SmallBitVector RegsUsed;
   VarList PhysicalRegisters[IceType_NUM];
   VarList PreservedGPRs;
   VarList PreservedSRegs;
 
   /// Helper class that understands the Calling Convention and register
   /// assignments. The first few integer type parameters can use r0-r3,
   /// regardless of their position relative to the floating-point/vector
   /// arguments in the argument list. Floating-point and vector arguments
   /// can use q0-q3 (aka d0-d7, s0-s15). For more information on the topic,
   /// see the ARM Architecture Procedure Calling Standards (AAPCS).
@@ skipping 17 matching lines @@
     /// appropriate register number. Note that, when Ty == IceType_i64, Reg will
     /// be an I64 register pair.
     bool argInGPR(Type Ty, RegNumT *Reg);
 
     /// argInVFP is to floating-point/vector types what argInGPR is for integer
     /// types.
     bool argInVFP(Type Ty, RegNumT *Reg);
 
   private:
     void discardUnavailableGPRsAndTheirAliases(CfgVector<RegNumT> *Regs);
-    llvm::SmallBitVector GPRegsUsed;
+    SmallBitVector GPRegsUsed;
     CfgVector<RegNumT> GPRArgs;
     CfgVector<RegNumT> I64Args;
 
     void discardUnavailableVFPRegs(CfgVector<RegNumT> *Regs);
-    llvm::SmallBitVector VFPRegsUsed;
+    SmallBitVector VFPRegsUsed;
     CfgVector<RegNumT> FP32Args;
     CfgVector<RegNumT> FP64Args;
     CfgVector<RegNumT> Vec128Args;
   };
 
 private:
   ENABLE_MAKE_UNIQUE;
 
   OperandARM32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt,
                                       Operand *Base);
 
   void postambleCtpop64(const InstCall *Instr);
   void preambleDivRem(const InstCall *Instr);
-  std::unordered_map<Operand *, void (TargetARM32::*)(const InstCall *Instr)>
+  CfgUnorderedMap<Operand *, void (TargetARM32::*)(const InstCall *Instr)>
       ARM32HelpersPreamble;
-  std::unordered_map<Operand *, void (TargetARM32::*)(const InstCall *Instr)>
+  CfgUnorderedMap<Operand *, void (TargetARM32::*)(const InstCall *Instr)>
       ARM32HelpersPostamble;
 
   class ComputationTracker {
   public:
     ComputationTracker() = default;
     ~ComputationTracker() = default;
 
     void forgetProducers() { KnownComputations.clear(); }
     void recordProducers(CfgNode *Node);
 
@@ skipping 36 matching lines @@
       // by this instruction. If liveness analysis is not performed (e.g., in
       // Om1 mode) IsLiveOut will never be set to false, and folding will be
       // disabled.
       bool IsLiveOut = true;
       int32_t NumUses = 0;
       Type ComputationType;
     };
 
     // ComputationMap maps a Variable number to a payload identifying which
     // instruction defined it.
-    using ComputationMap = std::unordered_map<SizeT, ComputationEntry>;
+    using ComputationMap = CfgUnorderedMap<SizeT, ComputationEntry>;
     ComputationMap KnownComputations;
   };
 
   ComputationTracker Computations;
 
   // AllowTemporaryWithNoReg indicates if TargetARM32::makeReg() can be invoked
   // without specifying a physical register. This is needed for creating unbound
   // temporaries during Ice -> ARM lowering, but before register allocation.
   // This a safe-guard that no unbound temporaries are created during the
   // legalization post-passes.
@@ skipping 57 matching lines @@
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H