Subzero. Performance tweaks.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 283 matching lines @@
 
 } // end of anonymous namespace
 
 TargetARM32::TargetARM32(Cfg *Func)
     : TargetLowering(Func), NeedSandboxing(SandboxingType == ST_NaCl),
       CPUFeatures(Func->getContext()->getFlags()) {}
 
 void TargetARM32::staticInit(GlobalContext *Ctx) {
   RegNumT::setLimit(RegARM32::Reg_NUM);
   // Limit this size (or do all bitsets need to be the same width)???
-  llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
-  llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
-  llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
-  llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
-  llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
-  llvm::SmallBitVector QtoSRegisters(RegARM32::Reg_NUM);
-  llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
+  SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
+  SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
+  SmallBitVector Float32Registers(RegARM32::Reg_NUM);
+  SmallBitVector Float64Registers(RegARM32::Reg_NUM);
+  SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
+  SmallBitVector QtoSRegisters(RegARM32::Reg_NUM);
+  SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
   const unsigned EncodedReg_q8 = RegARM32::RegTable[RegARM32::Reg_q8].Encoding;
   for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
     const auto &Entry = RegARM32::RegTable[i];
     IntegerRegisters[i] = Entry.IsInt;
     I64PairRegisters[i] = Entry.IsI64Pair;
     Float32Registers[i] = Entry.IsFP32;
     Float64Registers[i] = Entry.IsFP64;
     VectorRegisters[i] = Entry.IsVec128;
     RegisterAliases[i].resize(RegARM32::Reg_NUM);
     // TODO(eholk): It would be better to store a QtoS flag in the
@@ skipping 596 matching lines @@
   // We makeReg() here instead of getPhysicalRegister() because the latter ends
   // up creating multi-blocks temporaries that liveness fails to validate.
   auto *PC = makeReg(IceType_i32, RegARM32::Reg_pc);
 
   auto *AddPcReloc = RelocOffset::create(Ctx);
   AddPcReloc->setSubtract(true);
   auto *AddPcLabel = InstARM32Label::create(Func, this);
   AddPcLabel->setRelocOffset(AddPcReloc);
 
   const IceString EmitText = Name;
-  // We need a -8 in the relocation expression to account for the pc's value
-  // read by the first instruction emitted in Finish(PC).
-  auto *Imm8 = RelocOffset::create(Ctx, -8);
 
   auto *MovwReloc = RelocOffset::create(Ctx);
   auto *MovwLabel = InstARM32Label::create(Func, this);
   MovwLabel->setRelocOffset(MovwReloc);
 
   auto *MovtReloc = RelocOffset::create(Ctx);
   auto *MovtLabel = InstARM32Label::create(Func, this);
   MovtLabel->setRelocOffset(MovtReloc);
 
   // The EmitString for these constant relocatables have hardcoded offsets
   // attached to them. This could be dangerous if, e.g., we ever implemented
   // instruction scheduling but llvm-mc currently does not support
   //
   //   movw reg, #:lower16:(Symbol - Label - Number)
   //   movt reg, #:upper16:(Symbol - Label - Number)
   //
   // relocations.
-  auto *CRLower = Ctx->getConstantSym({MovwReloc, AddPcReloc, Imm8}, Name,
+  static constexpr RelocOffsetT PcOffset = -8;
+  auto *CRLower = Ctx->getConstantSym(PcOffset, {MovwReloc, AddPcReloc}, Name,
                                       EmitText + " -16", SuppressMangling);
-  auto *CRUpper = Ctx->getConstantSym({MovtReloc, AddPcReloc, Imm8}, Name,
+  auto *CRUpper = Ctx->getConstantSym(PcOffset, {MovtReloc, AddPcReloc}, Name,
                                       EmitText + " -12", SuppressMangling);
 
   Context.insert(MovwLabel);
   _movw(Register, CRLower);
   Context.insert(MovtLabel);
   _movt(Register, CRUpper);
   // PC = fake-def to keep liveness consistent.
   Context.insert<InstFakeDef>(PC);
   Context.insert(AddPcLabel);
   Finish(PC);
@@ skipping 473 matching lines @@
   // registers (as a side effect, this gives variables a second chance at
   // physical register assignment).
   //
   // A middle ground approach is to leverage sparsity and allocate one block of
   // space on the frame for globals (variables with multi-block lifetime), and
   // one block to share for locals (single-block lifetime).
 
   Context.init(Node);
   Context.setInsertPoint(Context.getCur());
 
-  llvm::SmallBitVector CalleeSaves =
-      getRegisterSet(RegSet_CalleeSave, RegSet_None);
-  RegsUsed = llvm::SmallBitVector(CalleeSaves.size());
+  SmallBitVector CalleeSaves = getRegisterSet(RegSet_CalleeSave, RegSet_None);
+  RegsUsed = SmallBitVector(CalleeSaves.size());
   VarList SortedSpilledVariables;
   size_t GlobalsSize = 0;
   // If there is a separate locals area, this represents that area. Otherwise
   // it counts any variable not counted by GlobalsSize.
   SpillAreaSizeBytes = 0;
   // If there is a separate locals area, this specifies the alignment for it.
   uint32_t LocalsSlotsAlignmentBytes = 0;
   // The entire spill locations area gets aligned to largest natural alignment
   // of the variables that have a spill slot.
   uint32_t SpillAreaAlignmentBytes = 0;
@@ skipping 35 matching lines @@
   }
   if (!MaybeLeafFunc) {
     CalleeSaves[RegARM32::Reg_lr] = true;
     RegsUsed[RegARM32::Reg_lr] = true;
   }
 
   // Make two passes over the used registers. The first pass records all the
   // used registers -- and their aliases. Then, we figure out which GPRs and
   // VFP S registers should be saved. We don't bother saving D/Q registers
   // because their uses are recorded as S regs uses.
-  llvm::SmallBitVector ToPreserve(RegARM32::Reg_NUM);
+  SmallBitVector ToPreserve(RegARM32::Reg_NUM);
   for (SizeT i = 0; i < CalleeSaves.size(); ++i) {
     if (NeedSandboxing && i == RegARM32::Reg_r9) {
       // r9 is never updated in sandboxed code.
       continue;
     }
     if (CalleeSaves[i] && RegsUsed[i]) {
       ToPreserve |= RegisterAliases[i];
     }
   }
 
@@ skipping 624 matching lines @@
       }
       Variable *BaseR = legalizeToReg(Base);
       return OperandARM32Mem::create(Func, SplitType, BaseR, Offset,
                                      Mem->getAddrMode());
     }
   }
   llvm::report_fatal_error("Unsupported operand type");
   return nullptr;
 }
 
-llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
-                                                 RegSetMask Exclude) const {
-  llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
+SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
+                                           RegSetMask Exclude) const {
+  SmallBitVector Registers(RegARM32::Reg_NUM);
 
   for (uint32_t i = 0; i < RegARM32::Reg_NUM; ++i) {
     const auto &Entry = RegARM32::RegTable[i];
     if (Entry.Scratch && (Include & RegSet_CallerSave))
       Registers[i] = true;
     if (Entry.Preserved && (Include & RegSet_CalleeSave))
       Registers[i] = true;
     if (Entry.StackPtr && (Include & RegSet_StackPointer))
       Registers[i] = true;
     if (Entry.FramePtr && (Include & RegSet_FramePointer))
@@ skipping 3887 matching lines @@
 
 void TargetARM32::postLower() {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
   markRedefinitions();
   Context.availabilityUpdate();
 }
 
 void TargetARM32::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<RegNumT> &Permutation,
-    const llvm::SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
+    const SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   (void)Permutation;
   (void)ExcludeRegisters;
   (void)Salt;
   UnimplementedError(Func->getContext()->getFlags());
 }
 
 void TargetARM32::emit(const ConstantInteger32 *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
@@ skipping 726 matching lines @@
       << ".eabi_attribute 42, 1   @ Tag_MPextension_use\n"
       << ".eabi_attribute 68, 1   @ Tag_Virtualization_use\n";
   if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
     Str << ".eabi_attribute 44, 2   @ Tag_DIV_use\n";
   }
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
-llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
-llvm::SmallBitVector
-    TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
-llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
+SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
+SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
+SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice