Subzero. Performance tweaks.

src/IceTargetLowering.cpp

 //===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 100 matching lines @@
 
 Variable *LoweringContext::availabilityGet(Operand *Src) const {
   assert(Src);
   if (Src == LastDest)
     return LastSrc;
   return nullptr;
 }
 
 namespace {
 
-void printRegisterSet(Ostream &Str, const llvm::SmallBitVector &Bitset,
+void printRegisterSet(Ostream &Str, const SmallBitVector &Bitset,
                       std::function<IceString(RegNumT)> getRegName,
                       const IceString &LineIndentString) {
   constexpr size_t RegistersPerLine = 16;
   size_t Count = 0;
   for (RegNumT RegNum : RegNumBVIter(Bitset)) {
     if (Count == 0) {
       Str << LineIndentString;
     } else {
       Str << ",";
     }
@@ skipping 23 matching lines @@
 }
 
 LLVM_ATTRIBUTE_NORETURN void badTargetFatalError(TargetArch Target) {
   llvm::report_fatal_error("Unsupported target: " +
                            std::string(targetArchString(Target)));
 }
 
 } // end of anonymous namespace
 
 void TargetLowering::filterTypeToRegisterSet(
-    GlobalContext *Ctx, int32_t NumRegs,
-    llvm::SmallBitVector TypeToRegisterSet[], size_t TypeToRegisterSetSize,
-    std::function<IceString(RegNumT)> getRegName,
+    GlobalContext *Ctx, int32_t NumRegs, SmallBitVector TypeToRegisterSet[],
+    size_t TypeToRegisterSetSize, std::function<IceString(RegNumT)> getRegName,
     std::function<IceString(RegClass)> getRegClassName) {
-  std::vector<llvm::SmallBitVector> UseSet(TypeToRegisterSetSize,
-                                           llvm::SmallBitVector(NumRegs));
-  std::vector<llvm::SmallBitVector> ExcludeSet(TypeToRegisterSetSize,
-                                               llvm::SmallBitVector(NumRegs));
+  std::vector<SmallBitVector> UseSet(TypeToRegisterSetSize,
+                                     SmallBitVector(NumRegs));
+  std::vector<SmallBitVector> ExcludeSet(TypeToRegisterSetSize,
+                                         SmallBitVector(NumRegs));
 
   std::unordered_map<IceString, RegNumT> RegNameToIndex;
   for (int32_t RegIndex = 0; RegIndex < NumRegs; ++RegIndex) {
     const auto RegNum = RegNumT::fromInt(RegIndex);
     RegNameToIndex[getRegName(RegNum)] = RegNum;
   }
 
   ClFlags::StringVector BadRegNames;
 
   // The processRegList function iterates across the RegNames vector.  Each
   // entry in the vector is a string of the form "<reg>" or "<class>:<reg>".
   // The register class and register number are computed, and the corresponding
   // bit is set in RegSet[][].  If "<class>:" is missing, then the bit is set
   // for all classes.
   auto processRegList = [&](const ClFlags::StringVector &RegNames,
-                            std::vector<llvm::SmallBitVector> &RegSet) {
+                            std::vector<SmallBitVector> &RegSet) {
     for (const IceString &RegClassAndName : RegNames) {
       IceString RClass;
       IceString RName;
       splitToClassAndName(RegClassAndName, &RClass, &RName);
       if (!RegNameToIndex.count(RName)) {
         BadRegNames.push_back(RName);
         continue;
       }
       const int32_t RegIndex = RegNameToIndex.at(RName);
       for (SizeT TypeIndex = 0; TypeIndex < TypeToRegisterSetSize;
@@ skipping 13 matching lines @@
     std::string Buffer;
     llvm::raw_string_ostream StrBuf(Buffer);
     StrBuf << "Unrecognized use/exclude registers:";
     for (const auto &RegName : BadRegNames)
       StrBuf << " " << RegName;
     llvm::report_fatal_error(StrBuf.str());
   }
 
   // Apply filters.
   for (size_t TypeIndex = 0; TypeIndex < TypeToRegisterSetSize; ++TypeIndex) {
-    llvm::SmallBitVector *TypeBitSet = &TypeToRegisterSet[TypeIndex];
-    llvm::SmallBitVector *UseBitSet = &UseSet[TypeIndex];
-    llvm::SmallBitVector *ExcludeBitSet = &ExcludeSet[TypeIndex];
+    SmallBitVector *TypeBitSet = &TypeToRegisterSet[TypeIndex];
+    SmallBitVector *UseBitSet = &UseSet[TypeIndex];
+    SmallBitVector *ExcludeBitSet = &ExcludeSet[TypeIndex];
     if (UseBitSet->any())
       *TypeBitSet = *UseBitSet;
     (*TypeBitSet).reset(*ExcludeBitSet);
   }
 
   // Display filtered register sets, if requested.
   if (BuildDefs::dump() && NumRegs &&
       (Ctx->getFlags().getVerbose() & IceV_AvailableRegs)) {
     Ostream &Str = Ctx->getStrDump();
     const IceString Indent = "  ";
@@ skipping 228 matching lines @@
 // performance testing.
 void TargetLowering::regAlloc(RegAllocKind Kind) {
   TimerMarker T(TimerStack::TT_regAlloc, Func);
   LinearScan LinearScan(Func);
   RegSetMask RegInclude = RegSet_None;
   RegSetMask RegExclude = RegSet_None;
   RegInclude |= RegSet_CallerSave;
   RegInclude |= RegSet_CalleeSave;
   if (hasFramePointer())
     RegExclude |= RegSet_FramePointer;
-  llvm::SmallBitVector RegMask = getRegisterSet(RegInclude, RegExclude);
+  SmallBitVector RegMask = getRegisterSet(RegInclude, RegExclude);
   bool Repeat = (Kind == RAK_Global && Ctx->getFlags().shouldRepeatRegAlloc());
   do {
     LinearScan.init(Kind);
     LinearScan.scan(RegMask, Ctx->getFlags().shouldRandomizeRegAlloc());
     if (!LinearScan.hasEvictions())
       Repeat = false;
     Kind = RAK_SecondChance;
   } while (Repeat);
   // TODO(stichnot): Run the register allocator one more time to do stack slot
   // coalescing.  The idea would be to initialize the Unhandled list with the
@@ skipping 48 matching lines @@
   // Instead of std::sort, we could do a bucket sort with log2(alignment) as
   // the buckets, if performance is an issue.
   std::sort(Dest.begin(), Dest.end(),
             [this](const Variable *V1, const Variable *V2) {
               return typeWidthInBytesOnStack(V1->getType()) >
                      typeWidthInBytesOnStack(V2->getType());
             });
 }
 
 void TargetLowering::getVarStackSlotParams(
-    VarList &SortedSpilledVariables, llvm::SmallBitVector &RegsUsed,
+    VarList &SortedSpilledVariables, SmallBitVector &RegsUsed,
     size_t *GlobalsSize, size_t *SpillAreaSizeBytes,
     uint32_t *SpillAreaAlignmentBytes, uint32_t *LocalsSlotsAlignmentBytes,
     std::function<bool(Variable *)> TargetVarHook) {
   const VariablesMetadata *VMetadata = Func->getVMetadata();
   llvm::BitVector IsVarReferenced(Func->getNumVariables());
   for (CfgNode *Node : Func->getNodes()) {
     for (Inst &Instr : Node->getInsts()) {
       if (Instr.isDeleted())
         continue;
       if (const Variable *Var = Instr.getDest())
@@ skipping 10 matching lines @@
   // gets its own slot, but "local" variable slots are reused across basic
   // blocks. E.g., if A and B are local to block 1 and C is local to block 2,
   // then C may share a slot with A or B.
   //
   // We cannot coalesce stack slots if this function calls a "returns twice"
   // function. In that case, basic blocks may be revisited, and variables local
   // to those basic blocks are actually live until after the called function
   // returns a second time.
   const bool SimpleCoalescing = !callsReturnsTwice();
 
-  std::vector<size_t> LocalsSize(Func->getNumNodes());
+  CfgVector<size_t> LocalsSize(Func->getNumNodes());
   const VarList &Variables = Func->getVariables();
   VarList SpilledVariables;
   for (Variable *Var : Variables) {
     if (Var->hasReg()) {
       // Don't consider a rematerializable variable to be an actual register use
       // (specifically of the frame pointer).  Otherwise, the prolog may decide
       // to save the frame pointer twice - once because of the explicit need for
       // a frame pointer, and once because of an active use of a callee-save
       // register.
       if (!Var->isRematerializable())
@@ skipping 77 matching lines @@
   // SpillAreaSizeBytes has accounted for the extra test padding. When
   // UseFramePointer is true, the offset depends on the padding, not just the
   // SpillAreaSizeBytes. On the other hand, when UseFramePointer is false, the
   // offsets depend on the gap between SpillAreaSizeBytes and
   // SpillAreaPaddingBytes, so we don't increment that.
   size_t TestPadding = Ctx->getFlags().getTestStackExtra();
   if (UsesFramePointer)
     SpillAreaPaddingBytes += TestPadding;
   size_t GlobalsSpaceUsed = SpillAreaPaddingBytes;
   size_t NextStackOffset = SpillAreaPaddingBytes;
-  std::vector<size_t> LocalsSize(Func->getNumNodes());
+  CfgVector<size_t> LocalsSize(Func->getNumNodes());
   const bool SimpleCoalescing = !callsReturnsTwice();
 
   for (Variable *Var : SortedSpilledVariables) {
     size_t Increment = typeWidthInBytesOnStack(Var->getType());
     if (SimpleCoalescing && VMetadata->isTracked(Var)) {
       if (VMetadata->isMultiBlock(Var)) {
         GlobalsSpaceUsed += Increment;
         NextStackOffset = GlobalsSpaceUsed;
       } else {
         SizeT NodeIndex = VMetadata->getLocalUseNode(Var)->getIndex();
@@ skipping 202 matching lines @@
   case Target_##X:                                                             \
     return ::X::createTargetHeaderLowering(Ctx);
 #include "llvm/Config/SZTargets.def"
 #undef SUBZERO_TARGET
   }
 }
 
 TargetHeaderLowering::~TargetHeaderLowering() = default;
 
 } // end of namespace Ice