[fullcodegen] Factor out EmitLoadStoreICSlot from archs.

src/full-codegen/mips/full-codegen-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #if V8_TARGET_ARCH_MIPS
 
 // Note on Mips implementation:
 //
 // The result_register() for mips is the 'v0' register, which is defined
 // by the ABI to contain function return values. However, the first
@@ skipping 4091 matching lines @@
 void FullCodeGenerator::ClearPendingMessage() {
   DCHECK(!result_register().is(a1));
   ExternalReference pending_message_obj =
       ExternalReference::address_of_pending_message_obj(isolate());
   __ LoadRoot(a1, Heap::kTheHoleValueRootIndex);
   __ li(at, Operand(pending_message_obj));
   __ sw(a1, MemOperand(at));
 }
 
 
-void FullCodeGenerator::EmitLoadStoreICSlot(FeedbackVectorSlot slot) {
-  DCHECK(!slot.IsInvalid());
-  __ li(VectorStoreICTrampolineDescriptor::SlotRegister(),
-        Operand(SmiFromSlot(slot)));
-}
-
 void FullCodeGenerator::DeferredCommands::EmitCommands() {
   DCHECK(!result_register().is(a1));
   __ Pop(result_register());  // Restore the accumulator.
   __ Pop(a1);                 // Get the token.
   for (DeferredCommand cmd : commands_) {
     Label skip;
     __ li(at, Operand(Smi::FromInt(cmd.token)));
     __ Branch(&skip, ne, a1, Operand(at));
     switch (cmd.command) {
       case kReturn:
@@ skipping 91 matching lines @@
          reinterpret_cast<uint32_t>(
              isolate->builtins()->OsrAfterStackCheck()->entry()));
   return OSR_AFTER_STACK_CHECK;
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS