Enable concurrent sweep on MIPS and ARM64.

runtime/vm/assembler_arm64.h

Index: runtime/vm/assembler_arm64.h
diff --git a/runtime/vm/assembler_arm64.h b/runtime/vm/assembler_arm64.h
index ff159d6566df04f2277b98cb889e9cde98735f09..14756255d5d3611330219f31cc01366b780cf652 100644
--- a/runtime/vm/assembler_arm64.h
+++ b/runtime/vm/assembler_arm64.h
@@ -757,6 +757,22 @@ class Assembler : public ValueObject {
     EmitLoadStoreRegPair(STP, rt, rt2, a, sz);
   }
 
+  void ldxr(Register rt, Register rn) {
+    // rt = value
+    // rn = address
+    EmitLoadStoreExclusive(LDXR, R31, rn, rt, kDoubleWord);
+  }
+  void stxr(Register rs, Register rt, Register rn) {
+    // rs = status (1 = failure, 0 = success)
+    // rt = value
+    // rn = address
+    EmitLoadStoreExclusive(STXR, rs, rn, rt, kDoubleWord);
+  }
+  void clrex() {
+    const int32_t encoding = static_cast<int32_t>(CLREX);
+    Emit(encoding);
+  }
+
   // Conditional select.
   void csel(Register rd, Register rn, Register rm, Condition cond) {
     EmitConditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord);
@@ -1719,6 +1735,24 @@ class Assembler : public ValueObject {
     Emit(encoding);
   }
 
+  void EmitLoadStoreExclusive(LoadStoreExclusiveOp op, Register rs, Register rn,
+                              Register rt, OperandSize sz = kDoubleWord) {
+    ASSERT(sz == kDoubleWord);
+    const int32_t size = B31 | B30;
+
+    ASSERT((rs != kNoRegister) && (rs != ZR));
+    ASSERT((rn != kNoRegister) && (rn != ZR));
+    ASSERT((rt != kNoRegister) && (rt != ZR));
+
+    const int32_t encoding =
+        op | size |
+        (static_cast<int32_t>(ConcreteRegister(rs)) << kRsShift) |
+        (static_cast<int32_t>(ConcreteRegister(rn)) << kRnShift) |
+        (static_cast<int32_t>(ConcreteRegister(rt)) << kRtShift);
+
+    Emit(encoding);
+  }
+
   void EmitLoadStoreReg(LoadStoreRegOp op, Register rt, Address a,
                         OperandSize sz) {
     const Register crt = ConcreteRegister(rt);