Enable concurrent sweep on MIPS and ARM64.

runtime/vm/disassembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 #include "platform/assert.h"
 
@@ skipping 316 matching lines @@
     PrintRegister(reg, R31IsZR);
     return 2;
   } else if (format[1] == 't') {  // 'rt: Rt register
     int reg = instr->RtField();
     PrintRegister(reg, R31IsZR);
     return 2;
   } else if (format[1] == 'a') {  // 'ra: Ra register
     int reg = instr->RaField();
     PrintRegister(reg, R31IsZR);
     return 2;
+  } else if (format[1] == 's') {  // 'rs: Rs register
+    int reg = instr->RsField();
+    PrintRegister(reg, R31IsZR);
+    return 2;
   }
   UNREACHABLE();
   return -1;
 }
 
 
 int ARM64Decoder::FormatVRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 'v');
   if (format[1] == 'd') {
     int reg = instr->VdField();
@@ skipping 388 matching lines @@
     Unknown(instr);
   }
   if (instr->Bit(30)) {
     Format(instr, "ldrx 'rt, 'pcldr");
   } else {
     Format(instr, "ldrw 'rt, 'pcldr");
   }
 }
 
 
+void ARM64Decoder::DecodeLoadStoreExclusive(Instr* instr) {
+  if ((instr->Bit(23) != 0) ||
+      (instr->Bit(21) != 0) ||
+      (instr->Bit(15) != 0)) {
+    Unknown(instr);
+  }
+  const int32_t size = instr->Bits(30, 2);
+  if (size != 3) {
+    Unknown(instr);
+  }
+
+  const bool is_load = instr->Bit(22) == 1;
+  if (is_load) {
+    Format(instr, "ldxr 'rt, 'rn");
+  } else {
+    Format(instr, "stxr 'rs, 'rt, 'rn");
+  }
+}
+
+
 void ARM64Decoder::DecodeAddSubImm(Instr* instr) {
   switch (instr->Bit(30)) {
     case 0: {
       if ((instr->RdField() == R31) && (instr->SField() == 1)) {
         Format(instr, "cmni'sf 'rn, 'imm12s");
       } else {
         if (((instr->RdField() == R31) || (instr->RnField() == R31)) &&
             (instr->Imm12Field() == 0) && (instr->Bit(29) == 0)) {
           Format(instr, "mov'sf 'rd, 'rn");
         } else {
@@ skipping 87 matching lines @@
   } else if ((instr->Bits(0, 2) == 0) && (instr->Bits(2, 3) == 0) &&
              (instr->Bits(21, 3) == 2)) {
     Format(instr, "hlt 'imm16");
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeSystem(Instr* instr) {
+  if (instr->InstructionBits() == CLREX) {
+    Format(instr, "clrex");
+    return;
+  }
+
   if ((instr->Bits(0, 8) == 0x1f) && (instr->Bits(12, 4) == 2) &&
       (instr->Bits(16, 3) == 3) && (instr->Bits(19, 2) == 0) &&
       (instr->Bit(21) == 0)) {
     if (instr->Bits(8, 4) == 0) {
       Format(instr, "nop");
     } else {
       Unknown(instr);
     }
   } else {
     Unknown(instr);
@@ skipping 81 matching lines @@
 }
 
 
 void ARM64Decoder::DecodeLoadStore(Instr* instr) {
   if (instr->IsLoadStoreRegOp()) {
     DecodeLoadStoreReg(instr);
   } else if (instr->IsLoadStoreRegPairOp()) {
     DecodeLoadStoreRegPair(instr);
   } else if (instr->IsLoadRegLiteralOp()) {
     DecodeLoadRegLiteral(instr);
+  } else if (instr->IsLoadStoreExclusiveOp()) {
+    DecodeLoadStoreExclusive(instr);
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeAddSubShiftExt(Instr* instr) {
   switch (instr->Bit(30)) {
     case 0: {
       if ((instr->RdField() == R31) && (instr->SFField())) {
@@ skipping 502 matching lines @@
   if (out_instr_size) {
     *out_instr_size = Instr::kInstrSize;
   }
 }
 
 #endif  // !PRODUCT
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM