Enable concurrent sweep on MIPS and ARM64.

runtime/vm/stub_code_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/code_generator.h"
 #include "vm/compiler.h"
@@ skipping 1048 matching lines @@
   __ lw(T2, FieldAddress(T0, Object::tags_offset()));
   __ andi(CMPRES1, T2, Immediate(1 << RawObject::kRememberedBit));
   __ beq(CMPRES1, ZR, &add_to_buffer);
   __ lw(T1, Address(SP, 0 * kWordSize));
   __ lw(T2, Address(SP, 1 * kWordSize));
   __ lw(T3, Address(SP, 2 * kWordSize));
   __ addiu(SP, SP, Immediate(3 * kWordSize));
   __ Ret();
 
   __ Bind(&add_to_buffer);
+  // Atomically set the remembered bit of the object header.
+  Label retry;
+  __ Bind(&retry);
+  __ ll(T2, FieldAddress(T0, Object::tags_offset()));
   __ ori(T2, T2, Immediate(1 << RawObject::kRememberedBit));
-  __ sw(T2, FieldAddress(T0, Object::tags_offset()));
+  __ sc(T2, FieldAddress(T0, Object::tags_offset()));
+  // T2 = 1 on success, 0 on failure.
+  __ beq(T2, ZR, &retry);
 
   // Load the StoreBuffer block out of the thread. Then load top_ out of the
   // StoreBufferBlock and add the address to the pointers_.
   __ lw(T1, Address(THR, Thread::store_buffer_block_offset()));
   __ lw(T2, Address(T1, StoreBufferBlock::top_offset()));
   __ sll(T3, T2, 2);
   __ addu(T3, T1, T3);
   __ sw(T0, Address(T3, StoreBufferBlock::pointers_offset()));
 
   // Increment top_ and check for overflow.
@@ skipping 1221 matching lines @@
   __ Bind(&miss);
   __ LoadIsolate(T2);
   __ lw(CODE_REG, Address(T2, Isolate::ic_miss_code_offset()));
   __ lw(T1, FieldAddress(CODE_REG, Code::entry_point_offset()));
   __ Ret();
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS