Enable concurrent sweep on MIPS and ARM64.

runtime/vm/simulator_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include <setjmp.h>  // NOLINT
 #include <stdlib.h>
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
@@ skipping 1155 matching lines @@
   SetExclusiveAccess(addr);
   return ReadW(addr, instr);
 }
 
 
 intptr_t Simulator::WriteExclusiveW(uword addr, intptr_t value, Instr* instr) {
   MutexLocker ml(exclusive_access_lock_);
   bool write_allowed = HasExclusiveAccessAndOpen(addr);
   if (write_allowed) {
     WriteW(addr, value, instr);
-    return 0;  // Success.
+    return 1;  // Success.
   }
-  return 1;  // Failure.
+  return 0;  // Failure.
 }
 
 
 uword Simulator::CompareExchange(uword* address,
                                  uword compare_value,
                                  uword new_value) {
   MutexLocker ml(exclusive_access_lock_);
   // We do not get a reservation as it would be guaranteed to be found when
   // writing below. No other thread is able to make a reservation while we
   // hold the lock.
@@ skipping 973 matching lines @@
         int32_t res = ReadHU(addr, instr);
         set_register(instr->RtField(), res);
       }
       break;
     }
     case LUI: {
       ASSERT(instr->RsField() == 0);
       set_register(instr->RtField(), instr->UImmField() << 16);
       break;
     }
+    case LL: {
+      // Format(instr, "ll 'rt, 'imms('rs)");
+      int32_t base_val = get_register(instr->RsField());
+      int32_t imm_val = instr->SImmField();
+      uword addr = base_val + imm_val;
+      if (Simulator::IsIllegalAddress(addr)) {
+        HandleIllegalAccess(addr, instr);
+      } else {
+        int32_t res = ReadExclusiveW(addr, instr);
+        set_register(instr->RtField(), res);
+      }
+      break;
+    }
     case LW: {
       // Format(instr, "lw 'rt, 'imms('rs)");
       int32_t base_val = get_register(instr->RsField());
       int32_t imm_val = instr->SImmField();
       uword addr = base_val + imm_val;
       if (Simulator::IsIllegalAddress(addr)) {
         HandleIllegalAccess(addr, instr);
       } else {
         int32_t res = ReadW(addr, instr);
         set_register(instr->RtField(), res);
@@ skipping 25 matching lines @@
       int32_t base_val = get_register(instr->RsField());
       int32_t imm_val = instr->SImmField();
       uword addr = base_val + imm_val;
       if (Simulator::IsIllegalAddress(addr)) {
         HandleIllegalAccess(addr, instr);
       } else {
         WriteB(addr, rt_val & 0xff);
       }
       break;
     }
+    case SC: {
+      // Format(instr, "sc 'rt, 'imms('rs)");
+      int32_t rt_val = get_register(instr->RtField());
+      int32_t base_val = get_register(instr->RsField());
+      int32_t imm_val = instr->SImmField();
+      uword addr = base_val + imm_val;
+      if (Simulator::IsIllegalAddress(addr)) {
+        HandleIllegalAccess(addr, instr);
+      } else {
+        intptr_t status = WriteExclusiveW(addr, rt_val, instr);
+        set_register(instr->RtField(), status);
+      }
+      break;
+    }
     case SLTI: {
       // Format(instr, "slti 'rt, 'rs, 'imms");
       int32_t rs_val = get_register(instr->RsField());
       int32_t imm_val = instr->SImmField();
       set_register(instr->RtField(), rs_val < imm_val ? 1 : 0);
       break;
     }
     case SLTIU: {
       // Format(instr, "sltiu 'rt, 'rs, 'imms");
       uint32_t rs_val = get_register(instr->RsField());
@@ skipping 284 matching lines @@
   set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception));
   set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace));
   buf->Longjmp();
 }
 
 }  // namespace dart
 
 #endif  // defined(USING_SIMULATOR)
 
 #endif  // defined TARGET_ARCH_MIPS