Enable concurrent sweep on MIPS and ARM64.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 739 matching lines @@
            (a.type() == Address::PairPreIndex));
     EmitLoadStoreRegPair(LDP, rt, rt2, a, sz);
   }
   void stp(Register rt, Register rt2, Address a, OperandSize sz = kDoubleWord) {
     ASSERT((a.type() == Address::PairOffset) ||
            (a.type() == Address::PairPostIndex) ||
            (a.type() == Address::PairPreIndex));
     EmitLoadStoreRegPair(STP, rt, rt2, a, sz);
   }
 
+  void ldxr(Register rt, Register rn) {

[zra, 2016/02/25 04:02:35]

As on ARM, clrex looks like it would be useful to add as well, for testing.

[rmacnak, 2016/02/25 23:31:46]

Done.

+    // rt = value
+    // rn = address
+    EmitLoadStoreExclusive(LDXR, R31, rn, rt, kDoubleWord);
+  }
+  void stxr(Register rs, Register rt, Register rn) {
+    // rs = status (1 = failure, 0 = success)
+    // rt = value
+    // rn = address
+    EmitLoadStoreExclusive(STXR, rs, rn, rt, kDoubleWord);
+  }
+
   // Conditional select.
   void csel(Register rd, Register rn, Register rm, Condition cond) {
     EmitConditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord);
   }
   void csinc(Register rd, Register rn, Register rm, Condition cond) {
     EmitConditionalSelect(CSINC, rd, rn, rm, cond, kDoubleWord);
   }
   void cinc(Register rd, Register rn, Condition cond) {
     csinc(rd, rn, rn, InvertCondition(cond));
   }
@@ skipping 937 matching lines @@
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(rd) << kRdShift) |
         (static_cast<int32_t>(hw_idx) << kHWShift) |
         (static_cast<int32_t>(imm.value() & 0xffff) << kImm16Shift);
     Emit(encoding);
   }
 
+  void EmitLoadStoreExclusive(LoadStoreExclusiveOp op, Register rs, Register rn,
+                              Register rt, OperandSize sz = kDoubleWord) {
+    ASSERT(sz == kDoubleWord);
+    const int32_t size = B31 | B30;
+
+    ASSERT(rs != kNoRegister);
+    ASSERT(rn != kNoRegister);
+    ASSERT(rt != kNoRegister);
+
+    const int32_t encoding =
+        op | size |
+        (static_cast<int32_t>(rs) << kRsShift) |
+        (static_cast<int32_t>(rn) << kRnShift) |
+        (static_cast<int32_t>(rt) << kRtShift);
+
+    Emit(encoding);
+  }
+
   void EmitLoadStoreReg(LoadStoreRegOp op, Register rt, Address a,
                         OperandSize sz) {
     const Register crt = ConcreteRegister(rt);
     const int32_t size = Log2OperandSizeBytes(sz);
     const int32_t encoding =
         op | ((size & 0x3) << kSzShift) |
         (static_cast<int32_t>(crt) << kRtShift) |
         a.encoding();
     Emit(encoding);
   }
@@ skipping 200 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_