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Issue 172133003: Harmony: optimize Math.clz32. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: fix Created 6 years, 10 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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874 case 0xA2: return "cpuid"; 874 case 0xA2: return "cpuid";
875 case 0xBE: return "movsx_b"; 875 case 0xBE: return "movsx_b";
876 case 0xBF: return "movsx_w"; 876 case 0xBF: return "movsx_w";
877 case 0xB6: return "movzx_b"; 877 case 0xB6: return "movzx_b";
878 case 0xB7: return "movzx_w"; 878 case 0xB7: return "movzx_w";
879 case 0xAF: return "imul"; 879 case 0xAF: return "imul";
880 case 0xA5: return "shld"; 880 case 0xA5: return "shld";
881 case 0xAD: return "shrd"; 881 case 0xAD: return "shrd";
882 case 0xAC: return "shrd"; // 3-operand version. 882 case 0xAC: return "shrd"; // 3-operand version.
883 case 0xAB: return "bts"; 883 case 0xAB: return "bts";
884 case 0xBD: return "bsr";
884 default: return NULL; 885 default: return NULL;
885 } 886 }
886 } 887 }
887 888
888 889
889 // Disassembled instruction '*instr' and writes it into 'out_buffer'. 890 // Disassembled instruction '*instr' and writes it into 'out_buffer'.
890 int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer, 891 int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
891 byte* instr) { 892 byte* instr) {
892 tmp_buffer_pos_ = 0; // starting to write as position 0 893 tmp_buffer_pos_ = 0; // starting to write as position 0
893 byte* data = instr; 894 byte* data = instr;
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1089 } else if ((f0byte & 0xF0) == 0x80) { 1090 } else if ((f0byte & 0xF0) == 0x80) {
1090 data += JumpConditional(data, branch_hint); 1091 data += JumpConditional(data, branch_hint);
1091 } else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 || 1092 } else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 ||
1092 f0byte == 0xB7 || f0byte == 0xAF) { 1093 f0byte == 0xB7 || f0byte == 0xAF) {
1093 data += 2; 1094 data += 2;
1094 data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data); 1095 data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data);
1095 } else if ((f0byte & 0xF0) == 0x90) { 1096 } else if ((f0byte & 0xF0) == 0x90) {
1096 data += SetCC(data); 1097 data += SetCC(data);
1097 } else if ((f0byte & 0xF0) == 0x40) { 1098 } else if ((f0byte & 0xF0) == 0x40) {
1098 data += CMov(data); 1099 data += CMov(data);
1100 } else if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) {
1101 // shrd, shld, bts
1102 data += 2;
1103 AppendToBuffer("%s ", f0mnem);
1104 int mod, regop, rm;
1105 get_modrm(*data, &mod, &regop, &rm);
1106 data += PrintRightOperand(data);
1107 if (f0byte == 0xAB) {
1108 AppendToBuffer(",%s", NameOfCPURegister(regop));
1109 } else {
1110 AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
1111 }
1112 } else if (f0byte == 0xBD) {
1113 data += 2;
1114 int mod, regop, rm;
1115 get_modrm(*data, &mod, &regop, &rm);
1116 AppendToBuffer("%s %s,", f0mnem, NameOfCPURegister(regop));
1117 data += PrintRightOperand(data);
1099 } else { 1118 } else {
1100 data += 2; 1119 UnimplementedInstruction();
1101 if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) {
1102 // shrd, shld, bts
1103 AppendToBuffer("%s ", f0mnem);
1104 int mod, regop, rm;
1105 get_modrm(*data, &mod, &regop, &rm);
1106 data += PrintRightOperand(data);
1107 if (f0byte == 0xAB) {
1108 AppendToBuffer(",%s", NameOfCPURegister(regop));
1109 } else {
1110 AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
1111 }
1112 } else {
1113 UnimplementedInstruction();
1114 }
1115 } 1120 }
1116 } 1121 }
1117 break; 1122 break;
1118 1123
1119 case 0x8F: 1124 case 0x8F:
1120 { data++; 1125 { data++;
1121 int mod, regop, rm; 1126 int mod, regop, rm;
1122 get_modrm(*data, &mod, &regop, &rm); 1127 get_modrm(*data, &mod, &regop, &rm);
1123 if (regop == eax) { 1128 if (regop == eax) {
1124 AppendToBuffer("pop "); 1129 AppendToBuffer("pop ");
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1599 int mod, regop, rm; 1604 int mod, regop, rm;
1600 get_modrm(*data, &mod, &regop, &rm); 1605 get_modrm(*data, &mod, &regop, &rm);
1601 AppendToBuffer("cvttss2si %s,", NameOfCPURegister(regop)); 1606 AppendToBuffer("cvttss2si %s,", NameOfCPURegister(regop));
1602 data += PrintRightXMMOperand(data); 1607 data += PrintRightXMMOperand(data);
1603 } else if (b2 == 0x5A) { 1608 } else if (b2 == 0x5A) {
1604 data += 3; 1609 data += 3;
1605 int mod, regop, rm; 1610 int mod, regop, rm;
1606 get_modrm(*data, &mod, &regop, &rm); 1611 get_modrm(*data, &mod, &regop, &rm);
1607 AppendToBuffer("cvtss2sd %s,", NameOfXMMRegister(regop)); 1612 AppendToBuffer("cvtss2sd %s,", NameOfXMMRegister(regop));
1608 data += PrintRightXMMOperand(data); 1613 data += PrintRightXMMOperand(data);
1609 } else if (b2 == 0x6F) { 1614 } else if (b2 == 0x6F) {
1610 data += 3; 1615 data += 3;
1611 int mod, regop, rm; 1616 int mod, regop, rm;
1612 get_modrm(*data, &mod, &regop, &rm); 1617 get_modrm(*data, &mod, &regop, &rm);
1613 AppendToBuffer("movdqu %s,", NameOfXMMRegister(regop)); 1618 AppendToBuffer("movdqu %s,", NameOfXMMRegister(regop));
1614 data += PrintRightXMMOperand(data); 1619 data += PrintRightXMMOperand(data);
1615 } else if (b2 == 0x7F) { 1620 } else if (b2 == 0x7F) {
1616 AppendToBuffer("movdqu "); 1621 AppendToBuffer("movdqu ");
1617 data += 3; 1622 data += 3;
1618 int mod, regop, rm; 1623 int mod, regop, rm;
1619 get_modrm(*data, &mod, &regop, &rm); 1624 get_modrm(*data, &mod, &regop, &rm);
1620 data += PrintRightXMMOperand(data); 1625 data += PrintRightXMMOperand(data);
1621 AppendToBuffer(",%s", NameOfXMMRegister(regop)); 1626 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1622 } else { 1627 } else {
1623 UnimplementedInstruction(); 1628 UnimplementedInstruction();
1624 } 1629 }
1625 } else if (*(data+1) == 0xA5) { 1630 } else if (*(data+1) == 0xA5) {
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1763 fprintf(f, " "); 1768 fprintf(f, " ");
1764 } 1769 }
1765 fprintf(f, " %s\n", buffer.start()); 1770 fprintf(f, " %s\n", buffer.start());
1766 } 1771 }
1767 } 1772 }
1768 1773
1769 1774
1770 } // namespace disasm 1775 } // namespace disasm
1771 1776
1772 #endif // V8_TARGET_ARCH_IA32 1777 #endif // V8_TARGET_ARCH_IA32
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