Chromium Code Reviews| Index: src/IceTargetLoweringMIPS32.cpp |
| diff --git a/src/IceTargetLoweringMIPS32.cpp b/src/IceTargetLoweringMIPS32.cpp |
| index f9ee059f2efca1b2f913fcb085cd15c7e46a15c3..381ddf88aae5f44496871aa7adca398597578725 100644 |
| --- a/src/IceTargetLoweringMIPS32.cpp |
| +++ b/src/IceTargetLoweringMIPS32.cpp |
| @@ -582,6 +582,7 @@ void TargetMIPS32::lowerInt64Arithmetic(const InstArithmetic *Instr, |
| case InstArithmetic::Or: |
| case InstArithmetic::Sub: |
| case InstArithmetic::Xor: |
| + case InstArithmetic::Mul: |
| break; |
| default: |
| UnimplementedLoweringError(this, Instr); |
| @@ -644,6 +645,22 @@ void TargetMIPS32::lowerInt64Arithmetic(const InstArithmetic *Instr, |
| _mov(DestHi, T_Hi); |
| return; |
| } |
| + case InstArithmetic::Mul: { |
| + auto *T_Lo = I32Reg(RegMIPS32::Reg_LO), *T_Hi = I32Reg(RegMIPS32::Reg_HI); |
| + auto *T1 = I32Reg(), *T2 = I32Reg(); |
| + auto *TM1 = I32Reg(), *TM2 = I32Reg(), *TM3 = I32Reg(), *TM4 = I32Reg(); |
| + _multu(T_Lo, Src0LoR, Src1LoR); |
| + Context.insert<InstFakeDef>(T_Hi, T_Lo); |
| + _mflo(T1, T_Lo); |
| + _mfhi(T2, T_Hi); |
| + _mov(DestLo, T1); |
| + _mul(TM1, Src0HiR, Src1LoR); |
|
John
2016/02/19 02:52:40
I'm late to the party, but what's the difference b
rkotlerimgtec
2016/02/19 04:50:25
mult is signed 64 bit result in Lo/Hi
mul is 32 bi
|
| + _mul(TM2, Src0LoR, Src1HiR); |
| + _addu(TM3, TM1, T2); |
| + _addu(TM4, TM3, TM2); |
| + _mov(DestHi, TM4); |
| + return; |
| + } |
| default: |
| UnimplementedLoweringError(this, Instr); |
| return; |