Subzero: implement 64 bit multiply in mips32

src/IceInstMIPS32.def

Index: src/IceInstMIPS32.def
diff --git a/src/IceInstMIPS32.def b/src/IceInstMIPS32.def
index c7eb47d5ba4caf42067564a7834abf8edad4fda7..fce37ac9e70c3d82930c2f6d471b788b4e987eb7 100644
--- a/src/IceInstMIPS32.def
+++ b/src/IceInstMIPS32.def
@@ -103,6 +103,10 @@
     ALIASES1(Reg_FP))                                                          \
   X(Reg_RA,       = Reg_ZERO + 31,  "ra",    0, 1, 0, 0, 0, 0, 0, 0, 0,        \
     ALIASES1(Reg_RA))                                                          \
+  X(Reg_LO,       = Reg_ZERO + 32,  "lo",    0, 0, 0, 0, 1, 0, 0, 0, 0,        \

[Jim Stichnoth, 2016/02/19 14:53:09]

The "encode" column should probably have some sentinel value like 0, since I'm
sure the values 32 and 33 don't actually appear as a 6-bit sequence in encoded
instructions that use these registers.

Also - for a separate CL - the values in the "encode" column should be constants
like 0,1,2,3,... and definitely not constexprs that depend on the RegNumT enum
value.

[Jim Stichnoth, 2016/02/19 14:53:09]

You have put 1's in the isInt column.  This makes it available to the register
allocator for normal integer variables, which is probably not what you want. 
Most likely these attributes should all be 0, like with the "zero" register.

[rkotlerimgtec, 2016/02/19 23:53:32]

Done.

[rkotlerimgtec, 2016/02/19 23:53:32]

Done.

+    ALIASES2(Reg_LO, Reg_LOHI))                                                \
+  X(Reg_HI,       = Reg_ZERO + 33,  "hi",    0, 0, 0, 0, 1, 0, 0, 0, 0,        \
+   ALIASES2(Reg_HI, Reg_LOHI))
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 // TODO(reed kotler): List FP registers etc.
@@ -142,6 +146,8 @@
     ALIASES3(Reg_S6, Reg_S7, Reg_S6S7))                                        \
   X(Reg_T8T9,  26, "t8, t9",   1, 0, 0, 0, 0, 1, 0, 0, 0,                      \
     ALIASES3(Reg_T8, Reg_T9, Reg_T8T9))                                        \
+  X(Reg_LOHI,  8, "lo, hi",   1, 0, 0, 0, 0, 1, 0, 0, 0,                       \

[Jim Stichnoth, 2016/02/19 14:53:09]

Same comments as above - 0's in all the bool columns, and a sentinel value like
0 for the encoded value instead of 8.

[rkotlerimgtec, 2016/02/19 23:53:32]

Done.

+    ALIASES3(Reg_LO, Reg_HI, Reg_LOHI))                                        \
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 
@@ -160,9 +166,9 @@
 #define REGMIPS32_TABLE_BOUNDS                                                 \
   /* val, init */                                                              \
   X(Reg_GPR_First, = Reg_ZERO)                                                 \
-  X(Reg_GPR_Last,  = Reg_RA)                                                   \
+  X(Reg_GPR_Last,  = Reg_HI)                                                   \
   X(Reg_I64PAIR_First, = Reg_V0V1)                                             \
-  X(Reg_I64PAIR_Last, = Reg_T8T9)                                              \
+  X(Reg_I64PAIR_Last, = Reg_LOHI)                                              \
 //define X(val, init)
 
 // TODO(reed kotler): add condition code tables, etc.