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1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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575 void TargetMIPS32::lowerInt64Arithmetic(const InstArithmetic *Instr, | 575 void TargetMIPS32::lowerInt64Arithmetic(const InstArithmetic *Instr, |
576 Variable *Dest, Operand *Src0, | 576 Variable *Dest, Operand *Src0, |
577 Operand *Src1) { | 577 Operand *Src1) { |
578 InstArithmetic::OpKind Op = Instr->getOp(); | 578 InstArithmetic::OpKind Op = Instr->getOp(); |
579 switch (Op) { | 579 switch (Op) { |
580 case InstArithmetic::Add: | 580 case InstArithmetic::Add: |
581 case InstArithmetic::And: | 581 case InstArithmetic::And: |
582 case InstArithmetic::Or: | 582 case InstArithmetic::Or: |
583 case InstArithmetic::Sub: | 583 case InstArithmetic::Sub: |
584 case InstArithmetic::Xor: | 584 case InstArithmetic::Xor: |
| 585 case InstArithmetic::Mul: |
585 break; | 586 break; |
586 default: | 587 default: |
587 UnimplementedLoweringError(this, Instr); | 588 UnimplementedLoweringError(this, Instr); |
588 return; | 589 return; |
589 } | 590 } |
590 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); | 591 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); |
591 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest)); | 592 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest)); |
592 Variable *Src0LoR = legalizeToReg(loOperand(Src0)); | 593 Variable *Src0LoR = legalizeToReg(loOperand(Src0)); |
593 Variable *Src1LoR = legalizeToReg(loOperand(Src1)); | 594 Variable *Src1LoR = legalizeToReg(loOperand(Src1)); |
594 Variable *Src0HiR = legalizeToReg(hiOperand(Src0)); | 595 Variable *Src0HiR = legalizeToReg(hiOperand(Src0)); |
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637 return; | 638 return; |
638 } | 639 } |
639 case InstArithmetic::Xor: { | 640 case InstArithmetic::Xor: { |
640 auto *T_Lo = I32Reg(), *T_Hi = I32Reg(); | 641 auto *T_Lo = I32Reg(), *T_Hi = I32Reg(); |
641 _xor(T_Lo, Src0LoR, Src1LoR); | 642 _xor(T_Lo, Src0LoR, Src1LoR); |
642 _mov(DestLo, T_Lo); | 643 _mov(DestLo, T_Lo); |
643 _xor(T_Hi, Src0HiR, Src1HiR); | 644 _xor(T_Hi, Src0HiR, Src1HiR); |
644 _mov(DestHi, T_Hi); | 645 _mov(DestHi, T_Hi); |
645 return; | 646 return; |
646 } | 647 } |
| 648 case InstArithmetic::Mul: { |
| 649 // TODO(rkotler): Make sure that mul has the side effect of clobbering |
| 650 // LO, HI. Check for any other LO, HI quirkiness in this section. |
| 651 auto *T_Lo = I32Reg(RegMIPS32::Reg_LO), *T_Hi = I32Reg(RegMIPS32::Reg_HI); |
| 652 auto *T1 = I32Reg(), *T2 = I32Reg(); |
| 653 auto *TM1 = I32Reg(), *TM2 = I32Reg(), *TM3 = I32Reg(), *TM4 = I32Reg(); |
| 654 _multu(T_Lo, Src0LoR, Src1LoR); |
| 655 Context.insert<InstFakeDef>(T_Hi, T_Lo); |
| 656 _mflo(T1, T_Lo); |
| 657 _mfhi(T2, T_Hi); |
| 658 _mov(DestLo, T1); |
| 659 _mul(TM1, Src0HiR, Src1LoR); |
| 660 _mul(TM2, Src0LoR, Src1HiR); |
| 661 _addu(TM3, TM1, T2); |
| 662 _addu(TM4, TM3, TM2); |
| 663 _mov(DestHi, TM4); |
| 664 return; |
| 665 } |
647 default: | 666 default: |
648 UnimplementedLoweringError(this, Instr); | 667 UnimplementedLoweringError(this, Instr); |
649 return; | 668 return; |
650 } | 669 } |
651 } | 670 } |
652 | 671 |
653 void TargetMIPS32::lowerArithmetic(const InstArithmetic *Instr) { | 672 void TargetMIPS32::lowerArithmetic(const InstArithmetic *Instr) { |
654 Variable *Dest = Instr->getDest(); | 673 Variable *Dest = Instr->getDest(); |
655 // We need to signal all the UnimplementedLoweringError errors before any | 674 // We need to signal all the UnimplementedLoweringError errors before any |
656 // legalization into new variables, otherwise Om1 register allocation may fail | 675 // legalization into new variables, otherwise Om1 register allocation may fail |
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1292 Str << "\t.set\t" | 1311 Str << "\t.set\t" |
1293 << "nomips16\n"; | 1312 << "nomips16\n"; |
1294 } | 1313 } |
1295 | 1314 |
1296 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; | 1315 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; |
1297 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; | 1316 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
1298 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 1317 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
1299 | 1318 |
1300 } // end of namespace MIPS32 | 1319 } // end of namespace MIPS32 |
1301 } // end of namespace Ice | 1320 } // end of namespace Ice |
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