Subzero: implement 64 bit multiply in mips32

src/IceRegistersMIPS32.h

 //===- subzero/src/IceRegistersMIPS32.h - Register information --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 26 matching lines @@
   REGMIPS32_TABLE_BOUNDS
 #undef X
 };
 
 /// An enum of GPR Registers. The enum value does match the encoding used
 /// to binary encode register operands in instructions.
 enum GPRRegister {
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
           isI64Pair, isFP32, isFP64, isVec128, alias_init)                     \
                                                                                \
-  Encoded_##val encode,
+  Encoded_##val = encode,
   REGMIPS32_GPR_TABLE
 #undef X
       Encoded_Not_GPR = -1
 };
 
 // TODO(jvoung): Floating point and vector registers...
 // Need to model overlap and difference in encoding too.
 
 static inline GPRRegister getEncodedGPR(RegNumT RegNum) {
   assert(int(Reg_GPR_First) <= int(RegNum));
   assert(unsigned(RegNum) <= Reg_GPR_Last);
   return GPRRegister(RegNum - Reg_GPR_First);
 }
 
 const char *getRegName(RegNumT RegNum);
 
 } // end of namespace RegMIPS32
 
 // Extend enum RegClass with MIPS32-specific register classes (if any).
 enum RegClassMIPS32 : uint8_t { RCMIPS32_NUM = RC_Target };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H