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1 //===- subzero/src/IceRegistersMIPS32.h - Register information --*- C++ -*-===// | 1 //===- subzero/src/IceRegistersMIPS32.h - Register information --*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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37 REGMIPS32_TABLE_BOUNDS | 37 REGMIPS32_TABLE_BOUNDS |
38 #undef X | 38 #undef X |
39 }; | 39 }; |
40 | 40 |
41 /// An enum of GPR Registers. The enum value does match the encoding used | 41 /// An enum of GPR Registers. The enum value does match the encoding used |
42 /// to binary encode register operands in instructions. | 42 /// to binary encode register operands in instructions. |
43 enum GPRRegister { | 43 enum GPRRegister { |
44 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 44 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
45 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 45 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
46 \ | 46 \ |
47 Encoded_##val encode, | 47 Encoded_##val = encode, |
48 REGMIPS32_GPR_TABLE | 48 REGMIPS32_GPR_TABLE |
49 #undef X | 49 #undef X |
50 Encoded_Not_GPR = -1 | 50 Encoded_Not_GPR = -1 |
51 }; | 51 }; |
52 | 52 |
53 // TODO(jvoung): Floating point and vector registers... | 53 // TODO(jvoung): Floating point and vector registers... |
54 // Need to model overlap and difference in encoding too. | 54 // Need to model overlap and difference in encoding too. |
55 | 55 |
56 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { | 56 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { |
57 assert(int(Reg_GPR_First) <= int(RegNum)); | 57 assert(int(Reg_GPR_First) <= int(RegNum)); |
58 assert(unsigned(RegNum) <= Reg_GPR_Last); | 58 assert(unsigned(RegNum) <= Reg_GPR_Last); |
59 return GPRRegister(RegNum - Reg_GPR_First); | 59 return GPRRegister(RegNum - Reg_GPR_First); |
60 } | 60 } |
61 | 61 |
62 const char *getRegName(RegNumT RegNum); | 62 const char *getRegName(RegNumT RegNum); |
63 | 63 |
64 } // end of namespace RegMIPS32 | 64 } // end of namespace RegMIPS32 |
65 | 65 |
66 // Extend enum RegClass with MIPS32-specific register classes (if any). | 66 // Extend enum RegClass with MIPS32-specific register classes (if any). |
67 enum RegClassMIPS32 : uint8_t { RCMIPS32_NUM = RC_Target }; | 67 enum RegClassMIPS32 : uint8_t { RCMIPS32_NUM = RC_Target }; |
68 | 68 |
69 } // end of namespace MIPS32 | 69 } // end of namespace MIPS32 |
70 } // end of namespace Ice | 70 } // end of namespace Ice |
71 | 71 |
72 #endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H | 72 #endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H |
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