Subzero: implement 64 bit multiply in mips32

src/IceInstMIPS32.cpp

 //===- subzero/src/IceInstMips32.cpp - Mips32 instruction implementation --===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
@@ skipping 38 matching lines @@
   return "TBD";
 }
 
 template <> const char *InstMIPS32Addiu::Opcode = "addiu";
 template <> const char *InstMIPS32Lui::Opcode = "lui";
 template <> const char *InstMIPS32La::Opcode = "la";
 // Three-addr ops
 template <> const char *InstMIPS32Add::Opcode = "add";
 template <> const char *InstMIPS32Addu::Opcode = "addu";
 template <> const char *InstMIPS32And::Opcode = "and";
+template <> const char *InstMIPS32Mfhi::Opcode = "mfhi";
+template <> const char *InstMIPS32Mflo::Opcode = "mflo";
+template <> const char *InstMIPS32Mthi::Opcode = "mthi";
+template <> const char *InstMIPS32Mtlo::Opcode = "mtlo";
 template <> const char *InstMIPS32Mul::Opcode = "mul";
+template <> const char *InstMIPS32Mult::Opcode = "mult";
+template <> const char *InstMIPS32Multu::Opcode = "multu";
 template <> const char *InstMIPS32Or::Opcode = "or";
 template <> const char *InstMIPS32Ori::Opcode = "ori";
 template <> const char *InstMIPS32Sltu::Opcode = "sltu";
 template <> const char *InstMIPS32Sub::Opcode = "sub";
 template <> const char *InstMIPS32Subu::Opcode = "subu";
 template <> const char *InstMIPS32Xor::Opcode = "xor";
 
+template <> void InstMIPS32Mflo::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  emitUnaryopGPRFLoHi(Opcode, this, Func);
+}
+
+template <> void InstMIPS32Mfhi::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  emitUnaryopGPRFLoHi(Opcode, this, Func);
+}
+
+template <> void InstMIPS32Mtlo::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  emitUnaryopGPRTLoHi(Opcode, this, Func);
+}
+
+template <> void InstMIPS32Mthi::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  emitUnaryopGPRTLoHi(Opcode, this, Func);
+}
+
+template <> void InstMIPS32Mult::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  emitThreeAddrLoHi(Opcode, this, Func);
+}
+
+template <> void InstMIPS32Multu::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  emitThreeAddrLoHi(Opcode, this, Func);
+}
+
 InstMIPS32Call::InstMIPS32Call(Cfg *Func, Variable *Dest, Operand *CallTarget)
     : InstMIPS32(Func, InstMIPS32::Call, 1, Dest) {
   HasSideEffects = true;
   addSource(CallTarget);
 }
 
 InstMIPS32Mov::InstMIPS32Mov(Cfg *Func, Variable *Dest, Operand *Src)
     : InstMIPS32(Func, InstMIPS32::Mov, 2, Dest) {
   auto *Dest64 = llvm::dyn_cast<Variable64On32>(Dest);
   auto *Src64 = llvm::dyn_cast<Variable64On32>(Src);
@@ skipping 41 matching lines @@
 void InstMIPS32::emitUnaryopGPR(const char *Opcode, const InstMIPS32 *Inst,
                                 const Cfg *Func) {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\t" << Opcode << "\t";
   Inst->getDest()->emit(Func);
   Str << ", ";
   Inst->getSrc(0)->emit(Func);
 }
+void InstMIPS32::emitUnaryopGPRFLoHi(const char *Opcode, const InstMIPS32 *Inst,
+                                     const Cfg *Func) {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  Str << "\t" << Opcode << "\t";
+  Inst->getDest()->emit(Func);
+}
+
+void InstMIPS32::emitUnaryopGPRTLoHi(const char *Opcode, const InstMIPS32 *Inst,
+                                     const Cfg *Func) {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  Str << "\t" << Opcode << "\t";
+  Inst->getSrc(0)->emit(Func);
+}
 
 void InstMIPS32::emitThreeAddr(const char *Opcode, const InstMIPS32 *Inst,
                                const Cfg *Func) {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 2);
   Str << "\t" << Opcode << "\t";
   Inst->getDest()->emit(Func);
   Str << ", ";
   Inst->getSrc(0)->emit(Func);
   Str << ", ";
   Inst->getSrc(1)->emit(Func);
 }
 
+void InstMIPS32::emitThreeAddrLoHi(const char *Opcode, const InstMIPS32 *Inst,
+                                   const Cfg *Func) {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(Inst->getSrcSize() == 2);
+  Str << "\t" << Opcode << "\t";
+  Inst->getSrc(0)->emit(Func);
+  Str << ", ";
+  Inst->getSrc(1)->emit(Func);
+}
+
 void InstMIPS32Ret::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   assert(getSrcSize() > 0);
   auto *RA = llvm::cast<Variable>(getSrc(0));
   assert(RA->hasReg());
   assert(RA->getRegNum() == RegMIPS32::Reg_RA);
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\t"
          "jr"
@@ skipping 168 matching lines @@
   }
 
   Str << "\t";
   getDest()->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice