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Issue 1716483003: Subzero: implement 64 bit multiply in mips32 (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: changes suggested by stichnot Created 4 years, 10 months ago
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1 //===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS32 insts --*- C++ -*-=== // 1 //===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS32 insts --*- C++ -*-=== //
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of MIPS32 instructions in the form of x-macros. 10 // This file defines properties of MIPS32 instructions in the form of x-macros.
(...skipping 21 matching lines...)
32 #define ALIASES4(r0, r1, r2, r3) \ 32 #define ALIASES4(r0, r1, r2, r3) \
33 {RegMIPS32::r0, RegMIPS32::r1, RegMIPS32::r2, RegMIPS32::r3} 33 {RegMIPS32::r0, RegMIPS32::r1, RegMIPS32::r2, RegMIPS32::r3}
34 #define ALIASES7(r0, r1, r2, r3, r4, r5, r6) \ 34 #define ALIASES7(r0, r1, r2, r3, r4, r5, r6) \
35 {RegMIPS32::r0, RegMIPS32::r1, RegMIPS32::r2, RegMIPS32::r3, RegMIPS32::r4,\ 35 {RegMIPS32::r0, RegMIPS32::r1, RegMIPS32::r2, RegMIPS32::r3, RegMIPS32::r4,\
36 RegMIPS32::r5,RegMIPS32::r6} 36 RegMIPS32::r5,RegMIPS32::r6}
37 #endif 37 #endif
38 38
39 #define REGMIPS32_GPR_TABLE \ 39 #define REGMIPS32_GPR_TABLE \
40 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 40 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
41 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 41 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
42 X(Reg_ZERO, = 0, "zero", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 42 X(Reg_ZERO, =0, "zero", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
43 ALIASES1(Reg_ZERO)) \ 43 ALIASES1(Reg_ZERO)) \
44 X(Reg_AT, = Reg_ZERO + 1, "at", 0, 0, 0, 0, 1, 0, 0, 0, 0, \ 44 X(Reg_AT, =1, "at", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
Jim Stichnoth 2016/02/20 00:03:59 As long as you're making the change to remove Reg_
rkotlerimgtec 2016/02/20 00:32:43 Done.
45 ALIASES1(Reg_AT)) \ 45 ALIASES1(Reg_AT)) \
46 X(Reg_V0, = Reg_ZERO + 2, "v0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 46 X(Reg_V0, =2, "v0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
47 ALIASES2(Reg_V0, Reg_V0V1)) \ 47 ALIASES2(Reg_V0, Reg_V0V1)) \
48 X(Reg_V1, = Reg_ZERO + 3, "v1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 48 X(Reg_V1, =3, "v1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
49 ALIASES2(Reg_V1, Reg_V0V1)) \ 49 ALIASES2(Reg_V1, Reg_V0V1)) \
50 X(Reg_A0, = Reg_ZERO + 4, "a0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 50 X(Reg_A0, =4, "a0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
51 ALIASES2(Reg_A0, Reg_A0A1)) \ 51 ALIASES2(Reg_A0, Reg_A0A1)) \
52 X(Reg_A1, = Reg_ZERO + 5, "a1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 52 X(Reg_A1, =5, "a1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
53 ALIASES2(Reg_A1, Reg_A0A1)) \ 53 ALIASES2(Reg_A1, Reg_A0A1)) \
54 X(Reg_A2, = Reg_ZERO + 6, "a2", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 54 X(Reg_A2, =6, "a2", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
55 ALIASES2(Reg_A2, Reg_A2A3)) \ 55 ALIASES2(Reg_A2, Reg_A2A3)) \
56 X(Reg_A3, = Reg_ZERO + 7, "a3", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 56 X(Reg_A3, =7, "a3", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
57 ALIASES2(Reg_A3, Reg_A2A3)) \ 57 ALIASES2(Reg_A3, Reg_A2A3)) \
58 X(Reg_T0, = Reg_ZERO + 8, "t0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 58 X(Reg_T0, =8, "t0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
59 ALIASES2(Reg_T0, Reg_T0T1)) \ 59 ALIASES2(Reg_T0, Reg_T0T1)) \
60 X(Reg_T1, = Reg_ZERO + 9, "t1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 60 X(Reg_T1, =9, "t1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
61 ALIASES2(Reg_T1, Reg_T0T1)) \ 61 ALIASES2(Reg_T1, Reg_T0T1)) \
62 X(Reg_T2, = Reg_ZERO + 10, "t2", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 62 X(Reg_T2, =10, "t2", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
63 ALIASES2(Reg_T2, Reg_T2T3)) \ 63 ALIASES2(Reg_T2, Reg_T2T3)) \
64 X(Reg_T3, = Reg_ZERO + 11, "t3", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 64 X(Reg_T3, =11, "t3", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
65 ALIASES2(Reg_T3, Reg_T2T3)) \ 65 ALIASES2(Reg_T3, Reg_T2T3)) \
66 X(Reg_T4, = Reg_ZERO + 12, "t4", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 66 X(Reg_T4, =12, "t4", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
67 ALIASES2(Reg_T4, Reg_T4T5)) \ 67 ALIASES2(Reg_T4, Reg_T4T5)) \
68 X(Reg_T5, = Reg_ZERO + 14, "t5", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 68 X(Reg_T5, =13, "t5", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
69 ALIASES2(Reg_T5, Reg_T4T5)) \ 69 ALIASES2(Reg_T5, Reg_T4T5)) \
70 X(Reg_T6, = Reg_ZERO + 14, "t6", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 70 X(Reg_T6, =14, "t6", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
71 ALIASES2(Reg_T6, Reg_T6T7)) \ 71 ALIASES2(Reg_T6, Reg_T6T7)) \
72 X(Reg_T7, = Reg_ZERO + 15, "t7", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 72 X(Reg_T7, =15, "t7", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
73 ALIASES2(Reg_T7, Reg_T6T7)) \ 73 ALIASES2(Reg_T7, Reg_T6T7)) \
74 X(Reg_S0, = Reg_ZERO + 16, "s0", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 74 X(Reg_S0, =16, "s0", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
75 ALIASES2(Reg_S0, Reg_S0S1)) \ 75 ALIASES2(Reg_S0, Reg_S0S1)) \
76 X(Reg_S1, = Reg_ZERO + 17, "s1", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 76 X(Reg_S1, =17, "s1", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
77 ALIASES2(Reg_S1, Reg_S0S1)) \ 77 ALIASES2(Reg_S1, Reg_S0S1)) \
78 X(Reg_S2, = Reg_ZERO + 18, "s2", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 78 X(Reg_S2, =18, "s2", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
79 ALIASES2(Reg_S2, Reg_S2S3)) \ 79 ALIASES2(Reg_S2, Reg_S2S3)) \
80 X(Reg_S3, = Reg_ZERO + 19, "s3", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 80 X(Reg_S3, =19, "s3", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
81 ALIASES2(Reg_S3, Reg_S2S3)) \ 81 ALIASES2(Reg_S3, Reg_S2S3)) \
82 X(Reg_S4, = Reg_ZERO + 20, "s4", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 82 X(Reg_S4, =20, "s4", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
83 ALIASES2(Reg_S4, Reg_S4S5)) \ 83 ALIASES2(Reg_S4, Reg_S4S5)) \
84 X(Reg_S5, = Reg_ZERO + 21, "s5", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 84 X(Reg_S5, =21, "s5", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
85 ALIASES2(Reg_S5, Reg_S4S5)) \ 85 ALIASES2(Reg_S5, Reg_S4S5)) \
86 X(Reg_S6, = Reg_ZERO + 22, "s6", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 86 X(Reg_S6, =22, "s6", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
87 ALIASES2(Reg_S6, Reg_S6S7)) \ 87 ALIASES2(Reg_S6, Reg_S6S7)) \
88 X(Reg_S7, = Reg_ZERO + 23, "s7", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 88 X(Reg_S7, =23, "s7", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
89 ALIASES2(Reg_S7, Reg_S6S7)) \ 89 ALIASES2(Reg_S7, Reg_S6S7)) \
90 X(Reg_T8, = Reg_ZERO + 23, "t8", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 90 X(Reg_T8, =24, "t8", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
91 ALIASES2(Reg_T8, Reg_T8T9)) \ 91 ALIASES2(Reg_T8, Reg_T8T9)) \
92 X(Reg_T9, = Reg_ZERO + 25, "t9", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 92 X(Reg_T9, =25, "t9", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
93 ALIASES2(Reg_T9, Reg_T8T9)) \ 93 ALIASES2(Reg_T9, Reg_T8T9)) \
94 X(Reg_K0, = Reg_ZERO + 26, "k0", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 94 X(Reg_K0, =26, "k0", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
95 ALIASES1(Reg_K0)) \ 95 ALIASES1(Reg_K0)) \
96 X(Reg_K1, = Reg_ZERO + 27, "k1", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 96 X(Reg_K1, =27, "k1", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
97 ALIASES1(Reg_K1)) \ 97 ALIASES1(Reg_K1)) \
98 X(Reg_GP, = Reg_ZERO + 28, "gp", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 98 X(Reg_GP, =28, "gp", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
99 ALIASES1(Reg_GP)) \ 99 ALIASES1(Reg_GP)) \
100 X(Reg_SP, = Reg_ZERO + 29, "sp", 0, 0, 1, 0, 0, 0, 0, 0, 0, \ 100 X(Reg_SP, =29, "sp", 0, 0, 1, 0, 0, 0, 0, 0, 0, \
101 ALIASES1(Reg_SP)) \ 101 ALIASES1(Reg_SP)) \
102 X(Reg_FP, = Reg_ZERO + 30, "fp", 0, 0, 0, 1, 0, 0, 0, 0, 0, \ 102 X(Reg_FP, =30, "fp", 0, 0, 0, 1, 0, 0, 0, 0, 0, \
103 ALIASES1(Reg_FP)) \ 103 ALIASES1(Reg_FP)) \
104 X(Reg_RA, = Reg_ZERO + 31, "ra", 0, 1, 0, 0, 0, 0, 0, 0, 0, \ 104 X(Reg_RA, =31, "ra", 0, 1, 0, 0, 0, 0, 0, 0, 0, \
105 ALIASES1(Reg_RA)) \ 105 ALIASES1(Reg_RA)) \
106 X(Reg_LO, =0, "lo", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
107 ALIASES2(Reg_LO, Reg_LOHI)) \
108 X(Reg_HI, =0, "hi", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
109 ALIASES2(Reg_HI, Reg_LOHI))
106 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 110 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
107 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 111 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
108 // TODO(reed kotler): List FP registers etc. 112 // TODO(reed kotler): List FP registers etc.
109 // Be able to grab even registers, and the corresponding odd register 113 // Be able to grab even registers, and the corresponding odd register
110 // for each even register. 114 // for each even register.
111 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 115 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
112 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 116 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
113 // The following defines a table with the available pairs of consecutive i32 117 // The following defines a table with the available pairs of consecutive i32
114 // GPRs starting at an even GPR that is not r14. Those are used to hold i64 118 // GPRs starting at an even GPR that is not r14. Those are used to hold i64
115 // variables for atomic memory operations. If one of the registers in the pair 119 // variables for atomic memory operations. If one of the registers in the pair
(...skipping 19 matching lines...)
135 X(Reg_S0S1, 16, "s0, s1", 0, 1, 0, 0, 0, 1, 0, 0, 0, \ 139 X(Reg_S0S1, 16, "s0, s1", 0, 1, 0, 0, 0, 1, 0, 0, 0, \
136 ALIASES3(Reg_S0, Reg_S1, Reg_S0S1)) \ 140 ALIASES3(Reg_S0, Reg_S1, Reg_S0S1)) \
137 X(Reg_S2S3, 18, "s2, s3", 0, 1, 0, 0, 0, 1, 0, 0, 0, \ 141 X(Reg_S2S3, 18, "s2, s3", 0, 1, 0, 0, 0, 1, 0, 0, 0, \
138 ALIASES3(Reg_S2, Reg_S3, Reg_S2S3)) \ 142 ALIASES3(Reg_S2, Reg_S3, Reg_S2S3)) \
139 X(Reg_S4S5, 20, "s4, s5", 0, 1, 0, 0, 0, 1, 0, 0, 0, \ 143 X(Reg_S4S5, 20, "s4, s5", 0, 1, 0, 0, 0, 1, 0, 0, 0, \
140 ALIASES3(Reg_S4, Reg_S5, Reg_S4S5)) \ 144 ALIASES3(Reg_S4, Reg_S5, Reg_S4S5)) \
141 X(Reg_S6S7, 22, "s6, s7", 0, 1, 0, 0, 0, 1, 0, 0, 0, \ 145 X(Reg_S6S7, 22, "s6, s7", 0, 1, 0, 0, 0, 1, 0, 0, 0, \
142 ALIASES3(Reg_S6, Reg_S7, Reg_S6S7)) \ 146 ALIASES3(Reg_S6, Reg_S7, Reg_S6S7)) \
143 X(Reg_T8T9, 26, "t8, t9", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 147 X(Reg_T8T9, 26, "t8, t9", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
144 ALIASES3(Reg_T8, Reg_T9, Reg_T8T9)) \ 148 ALIASES3(Reg_T8, Reg_T9, Reg_T8T9)) \
149 X(Reg_LOHI, 0, "lo, hi", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
150 ALIASES3(Reg_LO, Reg_HI, Reg_LOHI)) \
145 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 151 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
146 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 152 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
147 153
148 // We also provide a combined table, so that there is a namespace where 154 // We also provide a combined table, so that there is a namespace where
149 // all of the registers are considered and have distinct numberings. 155 // all of the registers are considered and have distinct numberings.
150 // This is in contrast to the above, where the "encode" is based on how 156 // This is in contrast to the above, where the "encode" is based on how
151 // the register numbers will be encoded in binaries and values can overlap. 157 // the register numbers will be encoded in binaries and values can overlap.
152 #define REGMIPS32_TABLE \ 158 #define REGMIPS32_TABLE \
153 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ 159 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
154 isFP32, isFP64, isVec128, alias_init */ \ 160 isFP32, isFP64, isVec128, alias_init */ \
155 REGMIPS32_GPR_TABLE \ 161 REGMIPS32_GPR_TABLE \
156 REGMIPS32_I64PAIR_TABLE 162 REGMIPS32_I64PAIR_TABLE
157 163
158 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 164 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
159 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 165 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
160 #define REGMIPS32_TABLE_BOUNDS \ 166 #define REGMIPS32_TABLE_BOUNDS \
161 /* val, init */ \ 167 /* val, init */ \
162 X(Reg_GPR_First, = Reg_ZERO) \ 168 X(Reg_GPR_First, = Reg_ZERO) \
163 X(Reg_GPR_Last, = Reg_RA) \ 169 X(Reg_GPR_Last, = Reg_HI) \
164 X(Reg_I64PAIR_First, = Reg_V0V1) \ 170 X(Reg_I64PAIR_First, = Reg_V0V1) \
165 X(Reg_I64PAIR_Last, = Reg_T8T9) \ 171 X(Reg_I64PAIR_Last, = Reg_LOHI) \
166 //define X(val, init) 172 //define X(val, init)
167 173
168 // TODO(reed kotler): add condition code tables, etc. 174 // TODO(reed kotler): add condition code tables, etc.
169 175
170 176
171 #endif // SUBZERO_SRC_ICEINSTMIPS32_DEF 177 #endif // SUBZERO_SRC_ICEINSTMIPS32_DEF
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