Subzero: implement 64 bit multiply in mips32

src/IceInstMIPS32.def

 //===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS32 insts --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of MIPS32 instructions in the form of x-macros.
@@ skipping 85 matching lines @@
   X(Reg_K1,       = Reg_ZERO + 27,  "k1",    0, 0, 0, 0, 0, 0, 0, 0, 0,        \
     ALIASES1(Reg_K1))                                                          \
   X(Reg_GP,       = Reg_ZERO + 28,  "gp",    0, 0, 0, 0, 0, 0, 0, 0, 0,        \
     ALIASES1(Reg_GP))                                                          \
   X(Reg_SP,       = Reg_ZERO + 29,  "sp",    0, 0, 1, 0, 0, 0, 0, 0, 0,        \
     ALIASES1(Reg_SP))                                                          \
   X(Reg_FP,       = Reg_ZERO + 30,  "fp",    0, 0, 0, 1, 0, 0, 0, 0, 0,        \
     ALIASES1(Reg_FP))                                                          \
   X(Reg_RA,       = Reg_ZERO + 31,  "ra",    0, 1, 0, 0, 0, 0, 0, 0, 0,        \
     ALIASES1(Reg_RA))                                                          \
+  X(Reg_LO,       = Reg_ZERO + 32,  "lo",    0, 0, 0, 0, 1, 0, 0, 0, 0,        \

[Jim Stichnoth, 2016/02/19 14:53:09]

The "encode" column should probably have some sentinel value like 0, since I'm
sure the values 32 and 33 don't actually appear as a 6-bit sequence in encoded
instructions that use these registers.

Also - for a separate CL - the values in the "encode" column should be constants
like 0,1,2,3,... and definitely not constexprs that depend on the RegNumT enum
value.

[Jim Stichnoth, 2016/02/19 14:53:09]

You have put 1's in the isInt column.  This makes it available to the register
allocator for normal integer variables, which is probably not what you want. 
Most likely these attributes should all be 0, like with the "zero" register.

[rkotlerimgtec, 2016/02/19 23:53:32]

Done.

[rkotlerimgtec, 2016/02/19 23:53:32]

Done.

+    ALIASES2(Reg_LO, Reg_LOHI))                                                \
+  X(Reg_HI,       = Reg_ZERO + 33,  "hi",    0, 0, 0, 0, 1, 0, 0, 0, 0,        \
+   ALIASES2(Reg_HI, Reg_LOHI))
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 // TODO(reed kotler): List FP registers etc.
 // Be able to grab even registers, and the corresponding odd register
 // for each even register.
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 // The following defines a table with the available pairs of consecutive i32
 // GPRs starting at an even GPR that is not r14. Those are used to hold i64
 // variables for atomic memory operations. If one of the registers in the pair
@@ skipping 19 matching lines @@
   X(Reg_S0S1,  16, "s0, s1",   0, 1, 0, 0, 0, 1, 0, 0, 0,                      \
     ALIASES3(Reg_S0, Reg_S1, Reg_S0S1))                                        \
   X(Reg_S2S3,  18, "s2, s3",   0, 1, 0, 0, 0, 1, 0, 0, 0,                      \
     ALIASES3(Reg_S2, Reg_S3, Reg_S2S3))                                        \
   X(Reg_S4S5,  20, "s4, s5",   0, 1, 0, 0, 0, 1, 0, 0, 0,                      \
     ALIASES3(Reg_S4, Reg_S5, Reg_S4S5))                                        \
   X(Reg_S6S7,  22, "s6, s7",   0, 1, 0, 0, 0, 1, 0, 0, 0,                      \
     ALIASES3(Reg_S6, Reg_S7, Reg_S6S7))                                        \
   X(Reg_T8T9,  26, "t8, t9",   1, 0, 0, 0, 0, 1, 0, 0, 0,                      \
     ALIASES3(Reg_T8, Reg_T9, Reg_T8T9))                                        \
+  X(Reg_LOHI,  8, "lo, hi",   1, 0, 0, 0, 0, 1, 0, 0, 0,                       \

[Jim Stichnoth, 2016/02/19 14:53:09]

Same comments as above - 0's in all the bool columns, and a sentinel value like
0 for the encoded value instead of 8.

[rkotlerimgtec, 2016/02/19 23:53:32]

Done.

+    ALIASES3(Reg_LO, Reg_HI, Reg_LOHI))                                        \
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 
 // We also provide a combined table, so that there is a namespace where
 // all of the registers are considered and have distinct numberings.
 // This is in contrast to the above, where the "encode" is based on how
 // the register numbers will be encoded in binaries and values can overlap.
 #define REGMIPS32_TABLE                                                        \
   /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt,         \
      isFP32, isFP64, isVec128, alias_init */                                   \
   REGMIPS32_GPR_TABLE                                                          \
   REGMIPS32_I64PAIR_TABLE
 
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 #define REGMIPS32_TABLE_BOUNDS                                                 \
   /* val, init */                                                              \
   X(Reg_GPR_First, = Reg_ZERO)                                                 \
-  X(Reg_GPR_Last,  = Reg_RA)                                                   \
+  X(Reg_GPR_Last,  = Reg_HI)                                                   \
   X(Reg_I64PAIR_First, = Reg_V0V1)                                             \
-  X(Reg_I64PAIR_Last, = Reg_T8T9)                                              \
+  X(Reg_I64PAIR_Last, = Reg_LOHI)                                              \
 //define X(val, init)
 
 // TODO(reed kotler): add condition code tables, etc.
 
 
 #endif // SUBZERO_SRC_ICEINSTMIPS32_DEF