Enables language tests for SIMMIPS.

runtime/vm/flow_graph_compiler_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_MIPS.
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/flow_graph_compiler.h"
 
 #include "lib/error.h"
@@ skipping 148 matching lines @@
 
 #define __ assembler()->
 
 
 // Fall through if bool_register contains null.
 void FlowGraphCompiler::GenerateBoolToJump(Register bool_register,
                                            Label* is_true,
                                            Label* is_false) {
   __ TraceSimMsg("BoolToJump");
   Label fall_through;
-  __ beq(bool_register, NULLREG, &fall_through);
+  __ BranchEqual(bool_register, reinterpret_cast<int32_t>(Object::null()),
+                 &fall_through);
   __ BranchEqual(bool_register, Bool::True(), is_true);
   __ b(is_false);
   __ Bind(&fall_through);
 }
 
 
 // A0: instance (must be preserved).
 // A1: instantiator type arguments (if used).
 RawSubtypeTestCache* FlowGraphCompiler::GenerateCallSubtypeTestStub(
     TypeTestStubKind test_kind,
     Register instance_reg,
     Register type_arguments_reg,
     Register temp_reg,
     Label* is_instance_lbl,
     Label* is_not_instance_lbl) {
   __ TraceSimMsg("CallSubtypeTestStub");
   ASSERT(instance_reg == A0);
   ASSERT(temp_reg == kNoRegister);  // Unused on MIPS.
   const SubtypeTestCache& type_test_cache =
       SubtypeTestCache::ZoneHandle(SubtypeTestCache::New());
   __ LoadObject(A2, type_test_cache);
   if (test_kind == kTestTypeOneArg) {
     ASSERT(type_arguments_reg == kNoRegister);
+    __ LoadImmediate(A1, reinterpret_cast<int32_t>(Object::null()));
     __ BranchLink(&StubCode::Subtype1TestCacheLabel());
-    __ delay_slot()->mov(A1, NULLREG);
   } else if (test_kind == kTestTypeTwoArgs) {
     ASSERT(type_arguments_reg == kNoRegister);
+    __ LoadImmediate(A1, reinterpret_cast<int32_t>(Object::null()));
     __ BranchLink(&StubCode::Subtype2TestCacheLabel());
-    __ delay_slot()->mov(A1, NULLREG);
   } else if (test_kind == kTestTypeThreeArgs) {
     ASSERT(type_arguments_reg == A1);
     __ BranchLink(&StubCode::Subtype3TestCacheLabel());
   } else {
     UNREACHABLE();
   }
   // Result is in V0: null -> not found, otherwise Bool::True or Bool::False.
   GenerateBoolToJump(V0, is_instance_lbl, is_not_instance_lbl);
   return type_test_cache.raw();
 }
@@ skipping 113 matching lines @@
   // Bool interface can be implemented only by core class Bool.
   if (type.IsBoolType()) {
     __ BranchEqual(kClassIdReg, kBoolCid, is_instance_lbl);
     __ b(is_not_instance_lbl);
     return false;
   }
   if (type.IsFunctionType()) {
     // Check if instance is a closure.
     __ LoadClassById(T1, kClassIdReg);
     __ lw(T1, FieldAddress(T1, Class::signature_function_offset()));
-    __ bne(T1, NULLREG, is_instance_lbl);
+    __ BranchNotEqual(T1, reinterpret_cast<int32_t>(Object::null()),
+                      is_instance_lbl);
   }
   // Custom checking for numbers (Smi, Mint, Bigint and Double).
   // Note that instance is not Smi (checked above).
   if (type.IsSubtypeOf(Type::Handle(Type::Number()), NULL)) {
     GenerateNumberTypeCheck(
         kClassIdReg, type, is_instance_lbl, is_not_instance_lbl);
     return false;
   }
   if (type.IsStringType()) {
     GenerateStringTypeCheck(kClassIdReg, is_instance_lbl, is_not_instance_lbl);
@@ skipping 47 matching lines @@
   __ TraceSimMsg("UninstantiatedTypeTest");
   __ Comment("UninstantiatedTypeTest");
   ASSERT(!type.IsInstantiated());
   // Skip check if destination is a dynamic type.
   if (type.IsTypeParameter()) {
     const TypeParameter& type_param = TypeParameter::Cast(type);
     // Load instantiator (or null) and instantiator type arguments on stack.
     __ lw(A1, Address(SP, 0));  // Get instantiator type arguments.
     // A1: instantiator type arguments.
     // Check if type argument is dynamic.
-    __ beq(A1, NULLREG, is_instance_lbl);
+    __ LoadImmediate(T7, reinterpret_cast<int32_t>(Object::null()));
+    __ beq(A1, T7, is_instance_lbl);
     // Can handle only type arguments that are instances of TypeArguments.
     // (runtime checks canonicalize type arguments).
     Label fall_through;
     __ LoadClassId(T2, A1);
     __ BranchNotEqual(T2, kTypeArgumentsCid, &fall_through);
     __ lw(T2,
         FieldAddress(A1, TypeArguments::type_at_offset(type_param.index())));
     // R2: concrete type of type.
     // Check if type argument is dynamic.
     __ BranchEqual(T2, Type::ZoneHandle(Type::DynamicType()), is_instance_lbl);
-    __ beq(T2, NULLREG, is_instance_lbl);
+    __ beq(T2, T7, is_instance_lbl);
     const Type& object_type = Type::ZoneHandle(Type::ObjectType());
     __ BranchEqual(T2, object_type, is_instance_lbl);
 
     // For Smi check quickly against int and num interfaces.
     Label not_smi;
     __ andi(CMPRES, A0, Immediate(kSmiTagMask));
     __ bne(CMPRES, ZR, &not_smi);  // Value is Smi?
     __ BranchEqual(T2, Type::ZoneHandle(Type::IntType()), is_instance_lbl);
     __ BranchEqual(T2, Type::ZoneHandle(Type::Number()), is_instance_lbl);
 
@@ skipping 54 matching lines @@
   __ TraceSimMsg("InlineInstanceof");
   __ Comment("InlineInstanceof");
   if (type.IsVoidType()) {
     // A non-null value is returned from a void function, which will result in a
     // type error. A null value is handled prior to executing this inline code.
     return SubtypeTestCache::null();
   }
   if (TypeCheckAsClassEquality(type)) {
     const intptr_t type_cid = Class::Handle(type.type_class()).id();
     const Register kInstanceReg = A0;
-    __ andi(T0, kInstanceReg, Immediate(kSmiTagMask));
+    __ andi(CMPRES, kInstanceReg, Immediate(kSmiTagMask));
     if (type_cid == kSmiCid) {
-      __ beq(T0, ZR, is_instance_lbl);
+      __ beq(CMPRES, ZR, is_instance_lbl);
     } else {
-      __ beq(T0, ZR, is_not_instance_lbl);
+      __ beq(CMPRES, ZR, is_not_instance_lbl);
       __ LoadClassId(T0, kInstanceReg);
       __ BranchEqual(T0, type_cid, is_instance_lbl);
     }
     __ b(is_not_instance_lbl);
     return SubtypeTestCache::null();
   }
   if (type.IsInstantiated()) {
     const Class& type_class = Class::ZoneHandle(type.type_class());
     // A Smi object cannot be the instance of a parameterized class.
     // A class equality check is only applicable with a dst type of a
@@ skipping 19 matching lines @@
       return SubtypeTestCache::null();
     }
   }
   return GenerateUninstantiatedTypeTest(token_pos,
                                         type,
                                         is_instance_lbl,
                                         is_not_instance_lbl);
 }
 
 
+// If instanceof type test cannot be performed successfully at compile time and
+// therefore eliminated, optimize it by adding inlined tests for:
+// - NULL -> return false.
+// - Smi -> compile time subtype check (only if dst class is not parameterized).
+// - Class equality (only if class is not parameterized).
+// Inputs:
+// - A0: object.
+// - A1: instantiator type arguments or raw_null.
+// - A2: instantiator or raw_null.
+// Returns:
+// - true or false in V0.
 void FlowGraphCompiler::GenerateInstanceOf(intptr_t token_pos,
                                            intptr_t deopt_id,
                                            const AbstractType& type,
                                            bool negate_result,
                                            LocationSummary* locs) {
-  UNIMPLEMENTED();
+  ASSERT(type.IsFinalized() && !type.IsMalformed());
+
+  // Preserve instantiator (A2) and its type arguments (A1).
+  __ addiu(SP, SP, Immediate(-2 * kWordSize));
+  __ sw(A2, Address(SP, 1 * kWordSize));
+  __ sw(A1, Address(SP, 0 * kWordSize));
+
+  Label is_instance, is_not_instance;
+  // If type is instantiated and non-parameterized, we can inline code
+  // checking whether the tested instance is a Smi.
+  if (type.IsInstantiated()) {
+    // A null object is only an instance of Object and dynamic, which has
+    // already been checked above (if the type is instantiated). So we can
+    // return false here if the instance is null (and if the type is
+    // instantiated).
+    // We can only inline this null check if the type is instantiated at compile
+    // time, since an uninstantiated type at compile time could be Object or
+    // dynamic at run time.
+    __ BranchEqual(A0, reinterpret_cast<int32_t>(Object::null()),
+                   &is_not_instance);
+  }
+
+  // Generate inline instanceof test.
+  SubtypeTestCache& test_cache = SubtypeTestCache::ZoneHandle();
+  test_cache = GenerateInlineInstanceof(token_pos, type,
+                                        &is_instance, &is_not_instance);
+
+  // test_cache is null if there is no fall-through.
+  Label done;
+  if (!test_cache.IsNull()) {
+    // Generate runtime call.
+    // Load instantiator (A2) and its type arguments (A1).
+    __ lw(A1, Address(SP, 0 * kWordSize));
+    __ lw(A2, Address(SP, 1 * kWordSize));
+
+    __ addiu(SP, SP, Immediate(-6 * kWordSize));
+    __ LoadObject(TMP, Object::ZoneHandle());
+    __ sw(TMP, Address(SP, 5 * kWordSize));  // Make room for the result.
+    __ sw(A0, Address(SP, 4 * kWordSize));  // Push the instance.
+    __ LoadObject(TMP, type);
+    __ sw(TMP, Address(SP, 3 * kWordSize));  // Push the type.
+    __ sw(A2, Address(SP, 2 * kWordSize));  // Push instantiator.
+    __ sw(A1, Address(SP, 1 * kWordSize));  // Push type arguments.
+    __ LoadObject(A0, test_cache);
+    __ sw(A0, Address(SP, 0 * kWordSize));
+    GenerateCallRuntime(token_pos, deopt_id, kInstanceofRuntimeEntry, locs);
+    // Pop the parameters supplied to the runtime entry. The result of the
+    // instanceof runtime call will be left as the result of the operation.
+    __ lw(T0, Address(SP, 5 * kWordSize));
+    __ addiu(SP, SP, Immediate(6 * kWordSize));
+    if (negate_result) {
+      __ LoadObject(V0, Bool::True());
+      __ bne(T0, V0, &done);
+      __ LoadObject(V0, Bool::False());
+    } else {
+      __ mov(V0, T0);
+    }
+    __ b(&done);
+  }
+  __ Bind(&is_not_instance);
+  __ LoadObject(V0, negate_result ? Bool::True() : Bool::False());
+  __ b(&done);
+
+  __ Bind(&is_instance);
+  __ LoadObject(V0, negate_result ? Bool::False() : Bool::True());
+  __ Bind(&done);
+  // Remove instantiator (A2) and its type arguments (A1).
+  __ Drop(2);
 }
 
 
 // Optimize assignable type check by adding inlined tests for:
 // - NULL -> return NULL.
 // - Smi -> compile time subtype check (only if dst class is not parameterized).
 // - Class equality (only if class is not parameterized).
 // Inputs:
 // - A0: instance being type checked.
 // - A1: instantiator type arguments or raw_null.
@@ skipping 14 matching lines @@
   ASSERT(dst_type.IsFinalized());
   // Assignable check is skipped in FlowGraphBuilder, not here.
   ASSERT(dst_type.IsMalformed() ||
          (!dst_type.IsDynamicType() && !dst_type.IsObjectType()));
   // Preserve instantiator and its type arguments.
   __ addiu(SP, SP, Immediate(-2 * kWordSize));
   __ sw(A2, Address(SP, 1 * kWordSize));
 
   // A null object is always assignable and is returned as result.
   Label is_assignable, runtime_call;
-  __ beq(A0, NULLREG, &is_assignable);
+
+  __ BranchEqual(A0, reinterpret_cast<int32_t>(Object::null()), &is_assignable);
   __ delay_slot()->sw(A1, Address(SP, 0 * kWordSize));
 
   if (!FLAG_eliminate_type_checks) {
     // If type checks are not eliminated during the graph building then
     // a transition sentinel can be seen here.
     __ BranchEqual(A0, Object::transition_sentinel(), &is_assignable);
   }
 
   // Generate throw new TypeError() if the type is malformed.
   if (dst_type.IsMalformed()) {
@@ skipping 216 matching lines @@
       // We do not use the final allocation index of the variable here, i.e.
       // scope->VariableAt(i)->index(), because captured variables still need
       // to be copied to the context that is not yet allocated.
       const intptr_t computed_param_pos = kFirstLocalSlotFromFp - param_pos;
       __ sw(T3, Address(FP, computed_param_pos * kWordSize));
     }
     delete[] opt_param;
     delete[] opt_param_position;
     // Check that T0 now points to the null terminator in the array descriptor.
     __ lw(T3, Address(T0));
-    __ beq(T3, NULLREG, &all_arguments_processed);
+    __ BranchEqual(T3, reinterpret_cast<int32_t>(Object::null()),
+                   &all_arguments_processed);
   } else {
     ASSERT(num_opt_pos_params > 0);
     __ Comment("There are optional positional parameters");
     __ lw(T2,
           FieldAddress(S4, ArgumentsDescriptor::positional_count_offset()));
     __ SmiUntag(T2);
     for (int i = 0; i < num_opt_pos_params; i++) {
       Label next_parameter;
       // Handle this optional positional parameter only if k or fewer positional
       // arguments have been passed, where k is param_pos, the position of this
@@ skipping 69 matching lines @@
   __ sll(T2, T2, 1);  // T2 is a Smi.
 
   __ Comment("Null arguments loop");
   Label null_args_loop, null_args_loop_exit;
   __ blez(T2, &null_args_loop_exit);
   __ delay_slot()->addiu(T1, FP,
                          Immediate((kParamEndSlotFromFp + 1) * kWordSize));
   __ Bind(&null_args_loop);
   __ addiu(T2, T2, Immediate(-kWordSize));
   __ addu(T3, T1, T2);
+  __ LoadImmediate(TMP, reinterpret_cast<int32_t>(Object::null()));
   __ bgtz(T2, &null_args_loop);
-  __ delay_slot()->sw(NULLREG, Address(T3));
+  __ delay_slot()->sw(TMP, Address(T3));
   __ Bind(&null_args_loop_exit);
 }
 
 
 void FlowGraphCompiler::GenerateInlinedGetter(intptr_t offset) {
   // RA: return address.
   // SP: receiver.
   // Sequence node has one return node, its input is load field node.
   __ lw(V0, Address(SP, 0 * kWordSize));
   __ lw(V0, Address(V0, offset - kHeapObjectTag));
   __ Ret();
 }
 
 
 void FlowGraphCompiler::GenerateInlinedSetter(intptr_t offset) {
   // RA: return address.
   // SP+1: receiver.
   // SP+0: value.
   // Sequence node has one store node and one return NULL node.
   __ lw(T0, Address(SP, 1 * kWordSize));  // Receiver.
   __ lw(T1, Address(SP, 0 * kWordSize));  // Value.
   __ StoreIntoObject(T0, FieldAddress(T0, offset), T1);
+  __ LoadImmediate(TMP, reinterpret_cast<int32_t>(Object::null()));
   __ Ret();
-  __ delay_slot()->mov(V0, NULLREG);
+  __ delay_slot()->mov(V0, TMP);
 }
 
 
 void FlowGraphCompiler::EmitFrameEntry() {
   const Function& function = parsed_function().function();
   if (CanOptimizeFunction() && function.is_optimizable()) {
     const bool can_optimize = !is_optimizing() || may_reoptimize();
     const Register function_reg = T0;
     if (can_optimize) {
       Label next;
@@ skipping 173 matching lines @@
   }
 
   // In unoptimized code, initialize (non-argument) stack allocated slots to
   // null. This does not cover the saved_args_desc_var slot.
   if (!is_optimizing() && (num_locals > 0)) {
     __ TraceSimMsg("Initialize spill slots");
     __ Comment("Initialize spill slots");
     const intptr_t slot_base = parsed_function().first_stack_local_index();
     for (intptr_t i = 0; i < num_locals; ++i) {
       // Subtract index i (locals lie at lower addresses than FP).
-      __ sw(NULLREG, Address(FP, (slot_base - i) * kWordSize));
+      __ LoadImmediate(TMP, reinterpret_cast<int32_t>(Object::null()));
+      __ sw(TMP, Address(FP, (slot_base - i) * kWordSize));
     }
   }
 
   if (FLAG_print_scopes) {
     // Print the function scope (again) after generating the prologue in order
     // to see annotations such as allocation indices of locals.
     if (FLAG_print_ast) {
       // Second printing.
       OS::Print("Annotated ");
     }
@@ skipping 214 matching lines @@
 void FlowGraphCompiler::EmitEqualityRegConstCompare(Register reg,
                                                     const Object& obj,
                                                     bool needs_number_check,
                                                     intptr_t token_pos) {
   __ TraceSimMsg("EqualityRegConstCompare");
   if (needs_number_check &&
       (obj.IsMint() || obj.IsDouble() || obj.IsBigint())) {
     __ addiu(SP, SP, Immediate(-2 * kWordSize));
     __ sw(reg, Address(SP, 1 * kWordSize));
     __ LoadObject(TMP1, obj);
+    __ sw(TMP1, Address(SP, 0 * kWordSize));
     __ BranchLink(&StubCode::IdenticalWithNumberCheckLabel());
     AddCurrentDescriptor(PcDescriptors::kRuntimeCall,
                          Isolate::kNoDeoptId,
                          token_pos);
-    __ delay_slot()->sw(TMP1, Address(SP, 0 * kWordSize));
     __ TraceSimMsg("EqualityRegConstCompare return");
     __ lw(reg, Address(SP, 1 * kWordSize));  // Restore 'reg'.
     __ addiu(SP, SP, Immediate(2 * kWordSize));  // Discard constant.
     return;
   }
   __ CompareObject(CMPRES, TMP1, reg, obj);
 }
 
 
 void FlowGraphCompiler::EmitEqualityRegRegCompare(Register left,
                                                   Register right,
                                                   bool needs_number_check,
                                                   intptr_t token_pos) {
   __ TraceSimMsg("EqualityRegRegCompare");
+  __ Comment("EqualityRegRegCompare");
   if (needs_number_check) {
     __ addiu(SP, SP, Immediate(-2 * kWordSize));
     __ sw(left, Address(SP, 1 * kWordSize));
+    __ sw(right, Address(SP, 0 * kWordSize));
     __ BranchLink(&StubCode::IdenticalWithNumberCheckLabel());
     AddCurrentDescriptor(PcDescriptors::kRuntimeCall,
                          Isolate::kNoDeoptId,
                          token_pos);
-    __ delay_slot()->sw(right, Address(SP, 0 * kWordSize));
     __ TraceSimMsg("EqualityRegRegCompare return");
     // Stub returns result in CMPRES. If it is 0, then left and right are equal.
     __ lw(right, Address(SP, 0 * kWordSize));
     __ lw(left, Address(SP, 1 * kWordSize));
     __ addiu(SP, SP, Immediate(2 * kWordSize));
   } else {
     __ slt(CMPRES, left, right);
     __ slt(TMP1, right, left);
   }
 }
 
 
 // Implement equality spec: if any of the arguments is null do identity check.
 // Fallthrough calls super equality.
 void FlowGraphCompiler::EmitSuperEqualityCallPrologue(Register result,
                                                       Label* skip_call) {
   Label check_identity, is_false, fall_through;
   __ TraceSimMsg("SuperEqualityCallPrologue");
   __ lw(result, Address(SP, 0 * kWordSize));  // Load right operand.
   __ lw(TMP1, Address(SP, 1 * kWordSize));  // Load left operand.
-  __ beq(result, NULLREG, &check_identity);  // Is right null?
-  __ bne(TMP1, NULLREG, &fall_through);  // If right is non-null, check left.
+  __ LoadImmediate(CMPRES, reinterpret_cast<int32_t>(Object::null()));
+  __ beq(result, CMPRES, &check_identity);  // Is right null?
+  __ bne(TMP1, CMPRES, &fall_through);  // If right is non-null, check left.
 
   __ Bind(&check_identity);
   __ bne(result, TMP1, &is_false);
   __ LoadObject(result, Bool::True());
   __ Drop(2);
   __ b(skip_call);
   __ Bind(&is_false);
   __ LoadObject(result, Bool::False());
   __ Drop(2);
   __ b(skip_call);
   __ Bind(&fall_through);
 }
 
 
 void FlowGraphCompiler::SaveLiveRegisters(LocationSummary* locs) {
   __ TraceSimMsg("SaveLiveRegisters");
   // TODO(vegorov): consider saving only caller save (volatile) registers.
-  const intptr_t fpu_registers = locs->live_registers()->fpu_registers();
-  if (fpu_registers > 0) {
-    UNIMPLEMENTED();
+  const intptr_t fpu_regs_count= locs->live_registers()->fpu_regs_count();
+  if (fpu_regs_count > 0) {
+    __ AddImmediate(SP, -(fpu_regs_count * kFpuRegisterSize));
+    // Store fpu registers with the lowest register number at the lowest
+    // address.
+    intptr_t offset = 0;
+    for (intptr_t reg_idx = 0; reg_idx < kNumberOfFpuRegisters; ++reg_idx) {
+      DRegister fpu_reg = static_cast<DRegister>(reg_idx);
+      if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) {
+        __ StoreDToOffset(fpu_reg, SP, offset);
+        offset += kFpuRegisterSize;
+      }
+    }
+    ASSERT(offset == (fpu_regs_count * kFpuRegisterSize));
   }
 
   // Store general purpose registers with the lowest register number at the
   // lowest address.
   const intptr_t cpu_registers = locs->live_registers()->cpu_registers();
   ASSERT((cpu_registers & ~kAllCpuRegistersList) == 0);
   const int register_count = Utils::CountOneBits(cpu_registers);
   int registers_pushed = 0;
 
   __ addiu(SP, SP, Immediate(-register_count * kWordSize));
@@ skipping 18 matching lines @@
 
   for (int i = 0; i < kNumberOfCpuRegisters; i++) {
     Register r = static_cast<Register>(i);
     if (locs->live_registers()->ContainsRegister(r)) {
       __ lw(r, Address(SP, registers_popped * kWordSize));
       registers_popped++;
     }
   }
   __ addiu(SP, SP, Immediate(register_count * kWordSize));
 
-  const intptr_t fpu_registers = locs->live_registers()->fpu_registers();
-  if (fpu_registers > 0) {
-    UNIMPLEMENTED();
+  const intptr_t fpu_regs_count = locs->live_registers()->fpu_regs_count();
+  if (fpu_regs_count > 0) {
+    // Fpu registers have the lowest register number at the lowest address.
+    intptr_t offset = 0;
+    for (intptr_t reg_idx = 0; reg_idx < kNumberOfFpuRegisters; ++reg_idx) {
+      DRegister fpu_reg = static_cast<DRegister>(reg_idx);
+      if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) {
+        __ LoadDFromOffset(fpu_reg, SP, offset);
+        offset += kFpuRegisterSize;
+      }
+    }
+    ASSERT(offset == (fpu_regs_count * kFpuRegisterSize));
+    __ AddImmediate(SP, offset);
   }
 }
 
 
 void FlowGraphCompiler::EmitTestAndCall(const ICData& ic_data,
                                         Register class_id_reg,
                                         intptr_t argument_count,
                                         const Array& argument_names,
                                         Label* deopt,
                                         intptr_t deopt_id,
                                         intptr_t token_index,
                                         LocationSummary* locs) {
   ASSERT(!ic_data.IsNull() && (ic_data.NumberOfChecks() > 0));
   Label match_found;
   const intptr_t len = ic_data.NumberOfChecks();
   GrowableArray<CidTarget> sorted(len);
   SortICDataByCount(ic_data, &sorted);
   ASSERT(class_id_reg != S4);
   ASSERT(len > 0);  // Why bother otherwise.
   const Array& arguments_descriptor =
       Array::ZoneHandle(ArgumentsDescriptor::New(argument_count,
                                                  argument_names));
   __ TraceSimMsg("EmitTestAndCall");
+  __ Comment("EmitTestAndCall");
   __ LoadObject(S4, arguments_descriptor);
   for (intptr_t i = 0; i < len; i++) {
     const bool is_last_check = (i == (len - 1));
     Label next_test;
     if (is_last_check) {
       __ BranchNotEqual(class_id_reg, sorted[i].cid, deopt);
     } else {
       __ BranchNotEqual(class_id_reg, sorted[i].cid, &next_test);
     }
     // Do not use the code from the function, but let the code be patched so
@@ skipping 12 matching lines @@
     __ Bind(&next_test);
   }
   __ Bind(&match_found);
 }
 
 
 void FlowGraphCompiler::EmitDoubleCompareBranch(Condition true_condition,
                                                 FpuRegister left,
                                                 FpuRegister right,
                                                 BranchInstr* branch) {
-  UNIMPLEMENTED();
+  ASSERT(branch != NULL);
+  __ Comment("DoubleCompareBranch");
+  assembler()->cund(left, right);
+  BlockEntryInstr* nan_result = (true_condition == NE) ?
+      branch->true_successor() : branch->false_successor();
+  assembler()->bc1t(GetJumpLabel(nan_result));
+
+  switch (true_condition) {
+    case EQ: assembler()->ceqd(left, right); break;
+    case LT: assembler()->coltd(left, right); break;
+    case LE: assembler()->coled(left, right); break;
+    case GT: assembler()->coltd(right, left); break;
+    case GE: assembler()->coled(right, left); break;
+    default: {
+      // Should only passing the above conditions to this function.
+      UNREACHABLE();
+      break;
+    }
+  }
+
+  assembler()->LoadImmediate(TMP, 1);
+  assembler()->movf(CMPRES, TMP);
+  assembler()->movt(CMPRES, ZR);
+  assembler()->mov(TMP, ZR);
+
+  // EmitBranchOnCondition expects ordering to be described by CMPRES, TMP1.
+  branch->EmitBranchOnCondition(this, EQ);
 }
 
 
 void FlowGraphCompiler::EmitDoubleCompareBool(Condition true_condition,
                                               FpuRegister left,
                                               FpuRegister right,
                                               Register result) {
-  UNIMPLEMENTED();
+  Label done;
+  __ Comment("DoubleCompareBool");
+  assembler()->LoadObject(result, Bool::False());
+  assembler()->cund(left, right);
+  assembler()->bc1t(&done);
+
+  switch (true_condition) {
+    case EQ: assembler()->ceqd(left, right); break;
+    case LT: assembler()->coltd(left, right); break;
+    case LE: assembler()->coled(left, right); break;
+    case GT: assembler()->coltd(right, left); break;
+    case GE: assembler()->coled(right, left); break;
+    default: {
+      // Should only passing the above conditions to this function.
+      UNREACHABLE();
+      break;
+    }
+  }
+
+  assembler()->bc1f(&done);  // False is already in result.
+  assembler()->LoadObject(result, Bool::True());
+  assembler()->Bind(&done);
 }
 
 
 FieldAddress FlowGraphCompiler::ElementAddressForIntIndex(intptr_t cid,
                                                           intptr_t index_scale,
                                                           Register array,
                                                           intptr_t index) {
   UNREACHABLE();
   return FieldAddress(array, index);
 }
@@ skipping 49 matching lines @@
     } else {
       ASSERT(destination.IsStackSlot());
       MoveMemoryToMemory(destination.ToStackSlotAddress(),
                          source.ToStackSlotAddress());
     }
   } else if (source.IsFpuRegister()) {
     if (destination.IsFpuRegister()) {
       __ movd(destination.fpu_reg(), source.fpu_reg());
     } else {
       if (destination.IsDoubleStackSlot()) {
-        __ sdc1(source.fpu_reg(), destination.ToStackSlotAddress());
+        const Address& addr = destination.ToStackSlotAddress();
+        int32_t offset = addr.get_offset();
+        __ StoreDToOffset(source.fpu_reg(), FP, offset);
       } else {
         ASSERT(destination.IsQuadStackSlot());
         UNIMPLEMENTED();
       }
     }
   } else if (source.IsDoubleStackSlot()) {
     if (destination.IsFpuRegister()) {
-      __ ldc1(destination.fpu_reg(), source.ToStackSlotAddress());
+      const Address &addr = source.ToStackSlotAddress();
+      const Register base = addr.get_base();
+      const int32_t offset = addr.get_offset();
+      __ LoadDFromOffset(destination.fpu_reg(), base, offset);
     } else {
       ASSERT(destination.IsDoubleStackSlot());
-      __ ldc1(FpuTMP, source.ToStackSlotAddress());
-      __ sdc1(FpuTMP, destination.ToStackSlotAddress());
+      const Address& saddr = source.ToStackSlotAddress();
+      const Address& daddr = destination.ToStackSlotAddress();
+      int32_t soffset = saddr.get_offset();
+      int32_t doffset = daddr.get_offset();
+      __ LoadDFromOffset(FpuTMP, FP, soffset);
+      __ StoreDToOffset(FpuTMP, FP, doffset);
     }
   } else if (source.IsQuadStackSlot()) {
     UNIMPLEMENTED();
   } else {
     ASSERT(source.IsConstant());
     if (destination.IsRegister()) {
       const Object& constant = source.constant();
       __ LoadObject(destination.reg(), constant);
     } else {
       ASSERT(destination.IsStackSlot());
@@ skipping 34 matching lines @@
            source.IsQuadStackSlot());
     bool double_width = destination.IsDoubleStackSlot() ||
                         source.IsDoubleStackSlot();
     DRegister reg = source.IsFpuRegister() ? source.fpu_reg()
                                            : destination.fpu_reg();
     const Address& slot_address = source.IsFpuRegister()
         ? destination.ToStackSlotAddress()
         : source.ToStackSlotAddress();
 
     if (double_width) {
-      __ ldc1(FpuTMP, slot_address);
-      __ sdc1(reg, slot_address);
+      const Register base = slot_address.get_base();
+      const int32_t offset = slot_address.get_offset();
+      __ LoadDFromOffset(FpuTMP, base, offset);
+      __ StoreDToOffset(reg, base, offset);
       __ movd(reg, FpuTMP);
     } else {
       UNIMPLEMENTED();
     }
   } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) {
     const Address& source_slot_address = source.ToStackSlotAddress();
     const Address& destination_slot_address = destination.ToStackSlotAddress();
+    const Register sbase = source_slot_address.get_base();
+    const int32_t soffset = source_slot_address.get_offset();
+    const Register dbase = destination_slot_address.get_base();
+    const int32_t doffset = destination_slot_address.get_offset();
 
     ScratchFpuRegisterScope ensure_scratch(this, FpuTMP);
-    __ ldc1(FpuTMP, source_slot_address);
-    __ ldc1(ensure_scratch.reg(), destination_slot_address);
-    __ sdc1(FpuTMP, destination_slot_address);
-    __ sdc1(ensure_scratch.reg(), source_slot_address);
+    __ LoadDFromOffset(FpuTMP, sbase, soffset);
+    __ LoadDFromOffset(ensure_scratch.reg(), dbase, doffset);
+    __ StoreDToOffset(FpuTMP, dbase, doffset);
+    __ StoreDToOffset(ensure_scratch.reg(), sbase, soffset);
   } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) {
     UNIMPLEMENTED();
   } else {
     UNREACHABLE();
   }
 
   // The swap of source and destination has executed a move from source to
   // destination.
   move->Eliminate();
 
@@ skipping 53 matching lines @@
 
 void ParallelMoveResolver::RestoreScratch(Register reg) {
   __ TraceSimMsg("ParallelMoveResolver::RestoreScratch");
   __ Pop(reg);
 }
 
 
 void ParallelMoveResolver::SpillFpuScratch(FpuRegister reg) {
   __ TraceSimMsg("ParallelMoveResolver::SpillFpuScratch");
   __ AddImmediate(SP, -kDoubleSize);
-  __ sdc1(reg, Address(SP));
+  __ StoreDToOffset(reg, SP, 0);
 }
 
 
 void ParallelMoveResolver::RestoreFpuScratch(FpuRegister reg) {
   __ TraceSimMsg("ParallelMoveResolver::RestoreFpuScratch");
-  __ ldc1(reg, Address(SP));
+  __ LoadDFromOffset(reg, SP, 0);
   __ AddImmediate(SP, kDoubleSize);
 }
 
 
 #undef __
 
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS