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Side by Side Diff: runtime/vm/assembler_mips.h

Issue 17131002: Enables language tests for SIMMIPS. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 6 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_ASSEMBLER_MIPS_H_ 5 #ifndef VM_ASSEMBLER_MIPS_H_
6 #define VM_ASSEMBLER_MIPS_H_ 6 #define VM_ASSEMBLER_MIPS_H_
7 7
8 #ifndef VM_ASSEMBLER_H_ 8 #ifndef VM_ASSEMBLER_H_
9 #error Do not include assembler_mips.h directly; use assembler.h instead. 9 #error Do not include assembler_mips.h directly; use assembler.h instead.
10 #endif 10 #endif
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60 uint32_t encoding() const { 60 uint32_t encoding() const {
61 ASSERT(Utils::IsInt(kImmBits, offset_)); 61 ASSERT(Utils::IsInt(kImmBits, offset_));
62 uint16_t imm_value = static_cast<uint16_t>(offset_); 62 uint16_t imm_value = static_cast<uint16_t>(offset_);
63 return (base_ << kRsShift) | imm_value; 63 return (base_ << kRsShift) | imm_value;
64 } 64 }
65 65
66 static bool CanHoldOffset(int32_t offset) { 66 static bool CanHoldOffset(int32_t offset) {
67 return Utils::IsInt(kImmBits, offset); 67 return Utils::IsInt(kImmBits, offset);
68 } 68 }
69 69
70 Register get_base() const { return base_; }
71 int32_t get_offset() const { return offset_; }
regis 2013/06/15 09:52:48 We usually do not write "get_" for getters: base()
zra 2013/06/17 15:58:15 Done.
72
70 private: 73 private:
71 Register base_; 74 Register base_;
72 int32_t offset_; 75 int32_t offset_;
73 }; 76 };
74 77
75 78
76 class FieldAddress : public Address { 79 class FieldAddress : public Address {
77 public: 80 public:
78 FieldAddress(Register base, int32_t disp) 81 FieldAddress(Register base, int32_t disp)
79 : Address(base, disp - kHeapObjectTag) { } 82 : Address(base, disp - kHeapObjectTag) { }
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432 } 435 }
433 436
434 void clo(Register rd, Register rs) { 437 void clo(Register rd, Register rs) {
435 EmitRType(SPECIAL2, rs, rd, rd, 0, CLO); 438 EmitRType(SPECIAL2, rs, rd, rd, 0, CLO);
436 } 439 }
437 440
438 void clz(Register rd, Register rs) { 441 void clz(Register rd, Register rs) {
439 EmitRType(SPECIAL2, rs, rd, rd, 0, CLZ); 442 EmitRType(SPECIAL2, rs, rd, rd, 0, CLZ);
440 } 443 }
441 444
445 // Convert a 32-bit float in fs to a 64-bit double in dd.
446 void cvtds(DRegister dd, FRegister fs) {
447 FRegister fd = static_cast<FRegister>(dd * 2);
448 EmitFpuRType(COP1, FMT_S, F0, fs, fd, COP1_CVT_D);
449 }
450
442 // Converts a 32-bit signed int in fs to a double in fd. 451 // Converts a 32-bit signed int in fs to a double in fd.
443 void cvtdw(DRegister dd, FRegister fs) { 452 void cvtdw(DRegister dd, FRegister fs) {
444 FRegister fd = static_cast<FRegister>(dd * 2); 453 FRegister fd = static_cast<FRegister>(dd * 2);
445 EmitFpuRType(COP1, FMT_W, F0, fs, fd, COP1_CVT_D); 454 EmitFpuRType(COP1, FMT_W, F0, fs, fd, COP1_CVT_D);
446 } 455 }
447 456
448 // Converts a 64-bit signed int in fs to a double in fd. 457 // Converts a 64-bit signed int in fs to a double in fd.
449 void cvtdl(DRegister dd, DRegister ds) { 458 void cvtdl(DRegister dd, DRegister ds) {
450 FRegister fs = static_cast<FRegister>(ds * 2); 459 FRegister fs = static_cast<FRegister>(ds * 2);
451 FRegister fd = static_cast<FRegister>(dd * 2); 460 FRegister fd = static_cast<FRegister>(dd * 2);
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546 void mov(Register rd, Register rs) { 555 void mov(Register rd, Register rs) {
547 or_(rd, rs, ZR); 556 or_(rd, rs, ZR);
548 } 557 }
549 558
550 void movd(DRegister dd, DRegister ds) { 559 void movd(DRegister dd, DRegister ds) {
551 FRegister fd = static_cast<FRegister>(dd * 2); 560 FRegister fd = static_cast<FRegister>(dd * 2);
552 FRegister fs = static_cast<FRegister>(ds * 2); 561 FRegister fs = static_cast<FRegister>(ds * 2);
553 EmitFpuRType(COP1, FMT_D, F0, fs, fd, COP1_MOV); 562 EmitFpuRType(COP1, FMT_D, F0, fs, fd, COP1_MOV);
554 } 563 }
555 564
565 // Move if floating point false.
566 void movf(Register rd, Register rs) {
567 EmitRType(SPECIAL, rs, R0, rd, 0, MOVCI);
568 }
569
556 void movn(Register rd, Register rs, Register rt) { 570 void movn(Register rd, Register rs, Register rt) {
557 EmitRType(SPECIAL, rs, rt, rd, 0, MOVN); 571 EmitRType(SPECIAL, rs, rt, rd, 0, MOVN);
558 } 572 }
559 573
574 // Move if floating point true.
575 void movt(Register rd, Register rs) {
576 EmitRType(SPECIAL, rs, R1, rd, 0, MOVCI);
577 }
578
560 void movz(Register rd, Register rs, Register rt) { 579 void movz(Register rd, Register rs, Register rt) {
561 EmitRType(SPECIAL, rs, rt, rd, 0, MOVZ); 580 EmitRType(SPECIAL, rs, rt, rd, 0, MOVZ);
562 } 581 }
563 582
564 void movs(FRegister fd, FRegister fs) { 583 void movs(FRegister fd, FRegister fs) {
565 EmitFpuRType(COP1, FMT_S, F0, fs, fd, COP1_MOV); 584 EmitFpuRType(COP1, FMT_S, F0, fs, fd, COP1_MOV);
566 } 585 }
567 586
568 void mtc1(Register rt, FRegister fs) { 587 void mtc1(Register rt, FRegister fs) {
569 Emit(COP1 << kOpcodeShift | 588 Emit(COP1 << kOpcodeShift |
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965 } 984 }
966 985
967 void SmiTag(Register reg) { 986 void SmiTag(Register reg) {
968 sll(reg, reg, kSmiTagSize); 987 sll(reg, reg, kSmiTagSize);
969 } 988 }
970 989
971 void SmiUntag(Register reg) { 990 void SmiUntag(Register reg) {
972 sra(reg, reg, kSmiTagSize); 991 sra(reg, reg, kSmiTagSize);
973 } 992 }
974 993
994 void StoreDToOffset(DRegister reg, Register base, int32_t offset) {
995 FRegister lo = static_cast<FRegister>(reg * 2);
996 FRegister hi = static_cast<FRegister>(reg * 2 + 1);
997 swc1(lo, Address(base, offset));
998 swc1(hi, Address(base, offset + kWordSize));
999 }
1000
1001 void LoadDFromOffset(DRegister reg, Register base, int32_t offset) {
1002 FRegister lo = static_cast<FRegister>(reg * 2);
1003 FRegister hi = static_cast<FRegister>(reg * 2 + 1);
1004 lwc1(lo, Address(base, offset));
1005 lwc1(hi, Address(base, offset + kWordSize));
1006 }
1007
975 void ReserveAlignedFrameSpace(intptr_t frame_space); 1008 void ReserveAlignedFrameSpace(intptr_t frame_space);
976 1009
977 // Create a frame for calling into runtime that preserves all volatile 1010 // Create a frame for calling into runtime that preserves all volatile
978 // registers. Frame's SP is guaranteed to be correctly aligned and 1011 // registers. Frame's SP is guaranteed to be correctly aligned and
979 // frame_space bytes are reserved under it. 1012 // frame_space bytes are reserved under it.
980 void EnterCallRuntimeFrame(intptr_t frame_space); 1013 void EnterCallRuntimeFrame(intptr_t frame_space);
981 void LeaveCallRuntimeFrame(); 1014 void LeaveCallRuntimeFrame();
982 1015
983 void LoadWordFromPoolOffset(Register rd, int32_t offset); 1016 void LoadWordFromPoolOffset(Register rd, int32_t offset);
984 void LoadObject(Register rd, const Object& object); 1017 void LoadObject(Register rd, const Object& object);
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1186 Register value, 1219 Register value,
1187 Label* no_update); 1220 Label* no_update);
1188 1221
1189 DISALLOW_ALLOCATION(); 1222 DISALLOW_ALLOCATION();
1190 DISALLOW_COPY_AND_ASSIGN(Assembler); 1223 DISALLOW_COPY_AND_ASSIGN(Assembler);
1191 }; 1224 };
1192 1225
1193 } // namespace dart 1226 } // namespace dart
1194 1227
1195 #endif // VM_ASSEMBLER_MIPS_H_ 1228 #endif // VM_ASSEMBLER_MIPS_H_
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