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Side by Side Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 1709793002: MIPS: [turbofan] Add RoundUint32ToFloat32 operator to Turbofan. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Rebased. Created 4 years, 10 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 85 matching lines...) Expand 10 before | Expand all | Expand 10 after
96 V(Mips64CeilWS) \ 96 V(Mips64CeilWS) \
97 V(Mips64TruncLS) \ 97 V(Mips64TruncLS) \
98 V(Mips64TruncLD) \ 98 V(Mips64TruncLD) \
99 V(Mips64TruncUwD) \ 99 V(Mips64TruncUwD) \
100 V(Mips64TruncUwS) \ 100 V(Mips64TruncUwS) \
101 V(Mips64TruncUlS) \ 101 V(Mips64TruncUlS) \
102 V(Mips64TruncUlD) \ 102 V(Mips64TruncUlD) \
103 V(Mips64CvtDW) \ 103 V(Mips64CvtDW) \
104 V(Mips64CvtSL) \ 104 V(Mips64CvtSL) \
105 V(Mips64CvtSW) \ 105 V(Mips64CvtSW) \
106 V(Mips64CvtSUw) \
106 V(Mips64CvtSUl) \ 107 V(Mips64CvtSUl) \
107 V(Mips64CvtDL) \ 108 V(Mips64CvtDL) \
108 V(Mips64CvtDUw) \ 109 V(Mips64CvtDUw) \
109 V(Mips64CvtDUl) \ 110 V(Mips64CvtDUl) \
110 V(Mips64Lb) \ 111 V(Mips64Lb) \
111 V(Mips64Lbu) \ 112 V(Mips64Lbu) \
112 V(Mips64Sb) \ 113 V(Mips64Sb) \
113 V(Mips64Lh) \ 114 V(Mips64Lh) \
114 V(Mips64Lhu) \ 115 V(Mips64Lhu) \
115 V(Mips64Sh) \ 116 V(Mips64Sh) \
(...skipping 36 matching lines...) Expand 10 before | Expand all | Expand 10 after
152 #define TARGET_ADDRESSING_MODE_LIST(V) \ 153 #define TARGET_ADDRESSING_MODE_LIST(V) \
153 V(MRI) /* [%r0 + K] */ \ 154 V(MRI) /* [%r0 + K] */ \
154 V(MRR) /* [%r0 + %r1] */ 155 V(MRR) /* [%r0 + %r1] */
155 156
156 157
157 } // namespace compiler 158 } // namespace compiler
158 } // namespace internal 159 } // namespace internal
159 } // namespace v8 160 } // namespace v8
160 161
161 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 162 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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