OLD | NEW |
1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
(...skipping 968 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
979 set_pc(instr->ImmPCOffsetTarget()); | 979 set_pc(instr->ImmPCOffsetTarget()); |
980 } | 980 } |
981 } | 981 } |
982 | 982 |
983 | 983 |
984 void Simulator::VisitUnconditionalBranchToRegister(Instruction* instr) { | 984 void Simulator::VisitUnconditionalBranchToRegister(Instruction* instr) { |
985 Instruction* target = reg<Instruction*>(instr->Rn()); | 985 Instruction* target = reg<Instruction*>(instr->Rn()); |
986 switch (instr->Mask(UnconditionalBranchToRegisterMask)) { | 986 switch (instr->Mask(UnconditionalBranchToRegisterMask)) { |
987 case BLR: { | 987 case BLR: { |
988 set_lr(instr->NextInstruction()); | 988 set_lr(instr->NextInstruction()); |
| 989 if (instr->Rn() == 31) { |
| 990 // BLR XZR is used as a guard for the constant pool. We should never hit |
| 991 // this, but if we do trap to allow debugging. |
| 992 Debug(); |
| 993 } |
989 // Fall through. | 994 // Fall through. |
990 } | 995 } |
991 case BR: | 996 case BR: |
992 case RET: set_pc(target); break; | 997 case RET: set_pc(target); break; |
993 default: UNIMPLEMENTED(); | 998 default: UNIMPLEMENTED(); |
994 } | 999 } |
995 } | 1000 } |
996 | 1001 |
997 | 1002 |
998 void Simulator::VisitTestBranch(Instruction* instr) { | 1003 void Simulator::VisitTestBranch(Instruction* instr) { |
(...skipping 2401 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3400 default: | 3405 default: |
3401 UNIMPLEMENTED(); | 3406 UNIMPLEMENTED(); |
3402 } | 3407 } |
3403 } | 3408 } |
3404 | 3409 |
3405 #endif // USE_SIMULATOR | 3410 #endif // USE_SIMULATOR |
3406 | 3411 |
3407 } } // namespace v8::internal | 3412 } } // namespace v8::internal |
3408 | 3413 |
3409 #endif // V8_TARGET_ARCH_A64 | 3414 #endif // V8_TARGET_ARCH_A64 |
OLD | NEW |