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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "src/compiler/code-generator.h" | 5 #include "src/compiler/code-generator.h" |
6 | 6 |
7 #include "src/compiler/code-generator-impl.h" | 7 #include "src/compiler/code-generator-impl.h" |
8 #include "src/compiler/gap-resolver.h" | 8 #include "src/compiler/gap-resolver.h" |
9 #include "src/compiler/node-matchers.h" | 9 #include "src/compiler/node-matchers.h" |
10 #include "src/compiler/osr.h" | 10 #include "src/compiler/osr.h" |
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1306 if (!IsNextInAssemblyOrder(target)) __ b(GetLabel(target)); | 1306 if (!IsNextInAssemblyOrder(target)) __ b(GetLabel(target)); |
1307 } | 1307 } |
1308 | 1308 |
1309 | 1309 |
1310 // Assembles boolean materializations after an instruction. | 1310 // Assembles boolean materializations after an instruction. |
1311 void CodeGenerator::AssembleArchBoolean(Instruction* instr, | 1311 void CodeGenerator::AssembleArchBoolean(Instruction* instr, |
1312 FlagsCondition condition) { | 1312 FlagsCondition condition) { |
1313 PPCOperandConverter i(this, instr); | 1313 PPCOperandConverter i(this, instr); |
1314 Label done; | 1314 Label done; |
1315 ArchOpcode op = instr->arch_opcode(); | 1315 ArchOpcode op = instr->arch_opcode(); |
1316 bool check_unordered = (op == kPPC_CmpDouble); | |
1317 CRegister cr = cr0; | 1316 CRegister cr = cr0; |
| 1317 int reg_value = -1; |
1318 | 1318 |
1319 // Overflow checked for add/sub only. | 1319 // Overflow checked for add/sub only. |
1320 DCHECK((condition != kOverflow && condition != kNotOverflow) || | 1320 DCHECK((condition != kOverflow && condition != kNotOverflow) || |
1321 (op == kPPC_AddWithOverflow32 || op == kPPC_SubWithOverflow32)); | 1321 (op == kPPC_AddWithOverflow32 || op == kPPC_SubWithOverflow32)); |
1322 | 1322 |
1323 // Materialize a full 32-bit 1 or 0 value. The result register is always the | 1323 // Materialize a full 32-bit 1 or 0 value. The result register is always the |
1324 // last output of the instruction. | 1324 // last output of the instruction. |
1325 DCHECK_NE(0u, instr->OutputCount()); | 1325 DCHECK_NE(0u, instr->OutputCount()); |
1326 Register reg = i.OutputRegister(instr->OutputCount() - 1); | 1326 Register reg = i.OutputRegister(instr->OutputCount() - 1); |
1327 | 1327 |
1328 Condition cond = FlagsConditionToCondition(condition); | 1328 Condition cond = FlagsConditionToCondition(condition); |
1329 switch (cond) { | 1329 if (op == kPPC_CmpDouble) { |
1330 case eq: | 1330 // check for unordered if necessary |
1331 case lt: | 1331 if (cond == le) { |
| 1332 reg_value = 0; |
1332 __ li(reg, Operand::Zero()); | 1333 __ li(reg, Operand::Zero()); |
1333 __ li(kScratchReg, Operand(1)); | 1334 __ bunordered(&done, cr); |
1334 __ isel(cond, reg, kScratchReg, reg, cr); | 1335 } else if (cond == gt) { |
1335 break; | 1336 reg_value = 1; |
1336 case ne: | |
1337 case ge: | |
1338 __ li(reg, Operand(1)); | 1337 __ li(reg, Operand(1)); |
1339 __ isel(NegateCondition(cond), reg, r0, reg, cr); | 1338 __ bunordered(&done, cr); |
1340 break; | 1339 } |
1341 case gt: | 1340 // Unnecessary for eq/lt & ne/ge since only FU bit will be set. |
1342 if (check_unordered) { | 1341 } |
1343 __ li(reg, Operand(1)); | 1342 |
| 1343 if (CpuFeatures::IsSupported(ISELECT)) { |
| 1344 switch (cond) { |
| 1345 case eq: |
| 1346 case lt: |
| 1347 case gt: |
| 1348 if (reg_value != 1) __ li(reg, Operand(1)); |
1344 __ li(kScratchReg, Operand::Zero()); | 1349 __ li(kScratchReg, Operand::Zero()); |
1345 __ bunordered(&done, cr); | |
1346 __ isel(cond, reg, reg, kScratchReg, cr); | 1350 __ isel(cond, reg, reg, kScratchReg, cr); |
1347 } else { | 1351 break; |
1348 __ li(reg, Operand::Zero()); | 1352 case ne: |
1349 __ li(kScratchReg, Operand(1)); | 1353 case ge: |
1350 __ isel(cond, reg, kScratchReg, reg, cr); | 1354 case le: |
1351 } | 1355 if (reg_value != 1) __ li(reg, Operand(1)); |
1352 break; | 1356 // r0 implies logical zero in this form |
1353 case le: | |
1354 if (check_unordered) { | |
1355 __ li(reg, Operand::Zero()); | |
1356 __ li(kScratchReg, Operand(1)); | |
1357 __ bunordered(&done, cr); | |
1358 __ isel(NegateCondition(cond), reg, r0, kScratchReg, cr); | |
1359 } else { | |
1360 __ li(reg, Operand(1)); | |
1361 __ isel(NegateCondition(cond), reg, r0, reg, cr); | 1357 __ isel(NegateCondition(cond), reg, r0, reg, cr); |
1362 } | 1358 break; |
1363 break; | |
1364 default: | 1359 default: |
1365 UNREACHABLE(); | 1360 UNREACHABLE(); |
1366 break; | 1361 break; |
| 1362 } |
| 1363 } else { |
| 1364 if (reg_value != 0) __ li(reg, Operand::Zero()); |
| 1365 __ b(NegateCondition(cond), &done, cr); |
| 1366 __ li(reg, Operand(1)); |
1367 } | 1367 } |
1368 __ bind(&done); | 1368 __ bind(&done); |
1369 } | 1369 } |
1370 | 1370 |
1371 | 1371 |
1372 void CodeGenerator::AssembleArchLookupSwitch(Instruction* instr) { | 1372 void CodeGenerator::AssembleArchLookupSwitch(Instruction* instr) { |
1373 PPCOperandConverter i(this, instr); | 1373 PPCOperandConverter i(this, instr); |
1374 Register input = i.InputRegister(0); | 1374 Register input = i.InputRegister(0); |
1375 for (size_t index = 2; index < instr->InputCount(); index += 2) { | 1375 for (size_t index = 2; index < instr->InputCount(); index += 2) { |
1376 __ Cmpi(input, Operand(i.InputInt32(index + 0)), r0); | 1376 __ Cmpi(input, Operand(i.InputInt32(index + 0)), r0); |
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1718 padding_size -= v8::internal::Assembler::kInstrSize; | 1718 padding_size -= v8::internal::Assembler::kInstrSize; |
1719 } | 1719 } |
1720 } | 1720 } |
1721 } | 1721 } |
1722 | 1722 |
1723 #undef __ | 1723 #undef __ |
1724 | 1724 |
1725 } // namespace compiler | 1725 } // namespace compiler |
1726 } // namespace internal | 1726 } // namespace internal |
1727 } // namespace v8 | 1727 } // namespace v8 |
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