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1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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551 Strh(rt, addr); | 551 Strh(rt, addr); |
552 } else if (r.IsInteger32()) { | 552 } else if (r.IsInteger32()) { |
553 Str(rt.W(), addr); | 553 Str(rt.W(), addr); |
554 } else { | 554 } else { |
555 ASSERT(rt.Is64Bits()); | 555 ASSERT(rt.Is64Bits()); |
556 Str(rt, addr); | 556 Str(rt, addr); |
557 } | 557 } |
558 } | 558 } |
559 | 559 |
560 | 560 |
| 561 bool MacroAssembler::ShouldEmitVeneer(int max_reachable_pc, int margin) { |
| 562 // Account for the branch around the veneers and the guard. |
| 563 int protection_offset = 2 * kInstructionSize; |
| 564 return pc_offset() > max_reachable_pc - margin - protection_offset - |
| 565 static_cast<int>(unresolved_branches_.size() * kMaxVeneerCodeSize); |
| 566 } |
| 567 |
| 568 |
| 569 void MacroAssembler::EmitVeneers(bool need_protection) { |
| 570 RecordComment("[ Veneers"); |
| 571 |
| 572 Label end; |
| 573 if (need_protection) { |
| 574 B(&end); |
| 575 } |
| 576 |
| 577 EmitVeneersGuard(); |
| 578 |
| 579 { |
| 580 InstructionAccurateScope scope(this); |
| 581 Label size_check; |
| 582 |
| 583 std::multimap<int, FarBranchInfo>::iterator it, it_to_delete; |
| 584 |
| 585 it = unresolved_branches_.begin(); |
| 586 while (it != unresolved_branches_.end()) { |
| 587 if (ShouldEmitVeneer(it->first)) { |
| 588 Instruction* branch = InstructionAt(it->second.pc_offset_); |
| 589 Label* label = it->second.label_; |
| 590 |
| 591 #ifdef DEBUG |
| 592 __ bind(&size_check); |
| 593 #endif |
| 594 // Patch the branch to point to the current position, and emit a branch |
| 595 // to the label. |
| 596 Instruction* veneer = reinterpret_cast<Instruction*>(pc_); |
| 597 RemoveBranchFromLabelLinkChain(branch, label, veneer); |
| 598 branch->SetImmPCOffsetTarget(veneer); |
| 599 b(label); |
| 600 #ifdef DEBUG |
| 601 ASSERT(SizeOfCodeGeneratedSince(&size_check) <= kMaxVeneerCodeSize); |
| 602 size_check.Unuse(); |
| 603 #endif |
| 604 |
| 605 it_to_delete = it++; |
| 606 unresolved_branches_.erase(it_to_delete); |
| 607 } else { |
| 608 ++it; |
| 609 } |
| 610 } |
| 611 } |
| 612 |
| 613 Bind(&end); |
| 614 |
| 615 RecordComment("]"); |
| 616 } |
| 617 |
| 618 |
| 619 void MacroAssembler::EmitVeneersGuard() { |
| 620 if (emit_debug_code()) { |
| 621 Unreachable(); |
| 622 } |
| 623 } |
| 624 |
| 625 |
| 626 void MacroAssembler::CheckVeneers(bool need_protection) { |
| 627 if (unresolved_branches_.empty()) { |
| 628 return; |
| 629 } |
| 630 |
| 631 CHECK(pc_offset() < unresolved_branches_first_limit()); |
| 632 int margin = kVeneerDistanceMargin; |
| 633 if (!need_protection) { |
| 634 // Prefer emitting veneers protected by an existing instruction. |
| 635 // The 4 divisor is a finger in the air guess. With a default margin of 2KB, |
| 636 // that leaves 512B = 128 instructions of extra margin to avoid requiring a |
| 637 // protective branch. |
| 638 margin += margin / 4; |
| 639 } |
| 640 if (ShouldEmitVeneer(unresolved_branches_first_limit(), margin)) { |
| 641 EmitVeneers(need_protection); |
| 642 } |
| 643 } |
| 644 |
| 645 |
| 646 bool MacroAssembler::NeedExtraInstructionsOrRegisterBranch( |
| 647 Label *label, ImmBranchType b_type) { |
| 648 bool need_longer_range = false; |
| 649 // There are two situations in which we care about the offset being out of |
| 650 // range: |
| 651 // - The label is bound but too far away. |
| 652 // - The label is not bound but linked, and the previous branch |
| 653 // instruction in the chain is too far away. |
| 654 if (label->is_bound() || label->is_linked()) { |
| 655 need_longer_range = |
| 656 !Instruction::IsValidImmPCOffset(b_type, label->pos() - pc_offset()); |
| 657 } |
| 658 if (!need_longer_range && !label->is_bound()) { |
| 659 int max_reachable_pc = pc_offset() + Instruction::ImmBranchRange(b_type); |
| 660 unresolved_branches_.insert( |
| 661 std::pair<int, FarBranchInfo>(max_reachable_pc, |
| 662 FarBranchInfo(pc_offset(), label))); |
| 663 } |
| 664 return need_longer_range; |
| 665 } |
| 666 |
| 667 |
| 668 void MacroAssembler::B(Label* label, Condition cond) { |
| 669 ASSERT(allow_macro_instructions_); |
| 670 ASSERT((cond != al) && (cond != nv)); |
| 671 |
| 672 Label done; |
| 673 bool need_extra_instructions = |
| 674 NeedExtraInstructionsOrRegisterBranch(label, CondBranchType); |
| 675 |
| 676 if (need_extra_instructions) { |
| 677 b(&done, InvertCondition(cond)); |
| 678 b(label); |
| 679 } else { |
| 680 b(label, cond); |
| 681 } |
| 682 CheckVeneers(!need_extra_instructions); |
| 683 bind(&done); |
| 684 } |
| 685 |
| 686 |
| 687 void MacroAssembler::Tbnz(const Register& rt, unsigned bit_pos, Label* label) { |
| 688 ASSERT(allow_macro_instructions_); |
| 689 |
| 690 Label done; |
| 691 bool need_extra_instructions = |
| 692 NeedExtraInstructionsOrRegisterBranch(label, TestBranchType); |
| 693 |
| 694 if (need_extra_instructions) { |
| 695 tbz(rt, bit_pos, &done); |
| 696 b(label); |
| 697 } else { |
| 698 tbnz(rt, bit_pos, label); |
| 699 } |
| 700 CheckVeneers(!need_extra_instructions); |
| 701 bind(&done); |
| 702 } |
| 703 |
| 704 |
| 705 void MacroAssembler::Tbz(const Register& rt, unsigned bit_pos, Label* label) { |
| 706 ASSERT(allow_macro_instructions_); |
| 707 |
| 708 Label done; |
| 709 bool need_extra_instructions = |
| 710 NeedExtraInstructionsOrRegisterBranch(label, TestBranchType); |
| 711 |
| 712 if (need_extra_instructions) { |
| 713 tbnz(rt, bit_pos, &done); |
| 714 b(label); |
| 715 } else { |
| 716 tbz(rt, bit_pos, label); |
| 717 } |
| 718 CheckVeneers(!need_extra_instructions); |
| 719 bind(&done); |
| 720 } |
| 721 |
| 722 |
| 723 void MacroAssembler::Cbnz(const Register& rt, Label* label) { |
| 724 ASSERT(allow_macro_instructions_); |
| 725 |
| 726 Label done; |
| 727 bool need_extra_instructions = |
| 728 NeedExtraInstructionsOrRegisterBranch(label, CompareBranchType); |
| 729 |
| 730 if (need_extra_instructions) { |
| 731 cbz(rt, &done); |
| 732 b(label); |
| 733 } else { |
| 734 cbnz(rt, label); |
| 735 } |
| 736 CheckVeneers(!need_extra_instructions); |
| 737 bind(&done); |
| 738 } |
| 739 |
| 740 |
| 741 void MacroAssembler::Cbz(const Register& rt, Label* label) { |
| 742 ASSERT(allow_macro_instructions_); |
| 743 |
| 744 Label done; |
| 745 bool need_extra_instructions = |
| 746 NeedExtraInstructionsOrRegisterBranch(label, CompareBranchType); |
| 747 |
| 748 if (need_extra_instructions) { |
| 749 cbnz(rt, &done); |
| 750 b(label); |
| 751 } else { |
| 752 cbz(rt, label); |
| 753 } |
| 754 CheckVeneers(!need_extra_instructions); |
| 755 bind(&done); |
| 756 } |
| 757 |
| 758 |
561 // Pseudo-instructions. | 759 // Pseudo-instructions. |
562 | 760 |
563 | 761 |
564 void MacroAssembler::Abs(const Register& rd, const Register& rm, | 762 void MacroAssembler::Abs(const Register& rd, const Register& rm, |
565 Label* is_not_representable, | 763 Label* is_not_representable, |
566 Label* is_representable) { | 764 Label* is_representable) { |
567 ASSERT(allow_macro_instructions_); | 765 ASSERT(allow_macro_instructions_); |
568 ASSERT(AreSameSizeAndType(rd, rm)); | 766 ASSERT(AreSameSizeAndType(rd, rm)); |
569 | 767 |
570 Cmp(rm, 1); | 768 Cmp(rm, 1); |
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4772 } | 4970 } |
4773 } | 4971 } |
4774 | 4972 |
4775 | 4973 |
4776 #undef __ | 4974 #undef __ |
4777 | 4975 |
4778 | 4976 |
4779 } } // namespace v8::internal | 4977 } } // namespace v8::internal |
4780 | 4978 |
4781 #endif // V8_TARGET_ARCH_A64 | 4979 #endif // V8_TARGET_ARCH_A64 |
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