Add fabs(<4 x float>) to the integrated ARM assembler.

tests_lit/assembler/arm32/vabs-vec.ll

Index: tests_lit/assembler/arm32/vabs-vec.ll
diff --git a/tests_lit/assembler/arm32/veor.ll b/tests_lit/assembler/arm32/vabs-vec.ll
similarity index 56%
copy from tests_lit/assembler/arm32/veor.ll
copy to tests_lit/assembler/arm32/vabs-vec.ll
index 8b138a1760b417ec33bdd49500e25fb9dd3618bc..c0cdf7c3314f44ea23025eeba744abe272a4c7d6 100644
--- a/tests_lit/assembler/arm32/veor.ll
+++ b/tests_lit/assembler/arm32/vabs-vec.ll
@@ -1,37 +1,41 @@
-; Show that we know how to translate veor. Does this by noting that
-; loading a double 0.0 introduces a veor.
+; Show that we translate intrinsics for fabs on vectors.

[Jim Stichnoth, 2016/02/17 03:58:39]

There's only one such intrinsic, right?  Maybe a comments like:

Show that we know how to translate the fabs intrinsic on vectors.

[Karl, 2016/02/17 17:51:44]

Done.

 
 ; REQUIRES: allow_dump
 
 ; Compile using standalone assembler.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
+; RUN:   -reg-use q5 \
 ; RUN:   | FileCheck %s --check-prefix=ASM
 
 ; Show bytes in assembled standalone code.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
+; RUN:   -reg-use q5 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
 ; Compile using integrated assembler.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
+; RUN:   -reg-use q5 \
 ; RUN:   | FileCheck %s --check-prefix=IASM
 
 ; Show bytes in assembled integrated code.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
+; RUN:   -reg-use q5 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
-define internal double @testVeor() {
-; ASM-LABEL: testVeor:
-; DIS: 00000000 <testVeor>:
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
 
-entry:
-; ASM: .LtestVeor$entry:
+define internal <4 x float> @_Z6myFabsDv4_f(<4 x float> %a) {
+; ASM-LABEL: _Z6myFabsDv4_f:
+; DIS-LABEL: {{.+}} <_Z6myFabsDv4_f>:
+; IASM-LABEL: _Z6myFabsDv4_f:
 
-  ret double 0.0
+  %x = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
 
-; ASM:  veor.f64        d0, d0, d0
-; DIS:    0:    f3000110
-; IASM-NOT: veor
+; ASM:            vabs.f32    q5, q5
+; DIS: {{.+}}:    f3b9a74a
+; IASM-NOT:       vabs.f32
 
+  ret <4 x float> %x
 }