Add fabs(<4 x float>) to the integrated ARM assembler.

tests_lit/assembler/arm32/vabs-vec.ll

-; Test the "vmrs APSR_nzcv, FPSCR" form of the VMRS instruction.
+; Show that we know how to translate the fabs intrinsic on float vectors.
 
 ; REQUIRES: allow_dump
 
 ; Compile using standalone assembler.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
+; RUN:   -reg-use q5 \
 ; RUN:   | FileCheck %s --check-prefix=ASM
 
 ; Show bytes in assembled standalone code.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
+; RUN:   -reg-use q5 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
 ; Compile using integrated assembler.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
+; RUN:   -reg-use q5 \
 ; RUN:   | FileCheck %s --check-prefix=IASM
 
 ; Show bytes in assembled integrated code.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
+; RUN:   -reg-use q5 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
-define internal i32 @testVmrsASPR_nzcv() {
-; ASM-LABEL: testVmrsASPR_nzcv:
-; DIS-LABEL: 00000000 <testVmrsASPR_nzcv>:
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
 
-entry:
-; ASM: .LtestVmrsASPR_nzcv$entry:
+define internal <4 x float> @_Z6myFabsDv4_f(<4 x float> %a) {
+; ASM-LABEL: _Z6myFabsDv4_f:
+; DIS-LABEL: {{.+}} <_Z6myFabsDv4_f>:
+; IASM-LABEL: _Z6myFabsDv4_f:
 
-  %test = fcmp olt float 0.0, 0.0
+  %x = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
 
-; ASM:  vmrs    APSR_nzcv, FPSCR
-; DIS:   14:    eef1fa10
-; IASM-NOT: vmrs
+; ASM:            vabs.f32    q5, q5
+; DIS: {{.+}}:    f3b9a74a
+; IASM-NOT:       vabs.f32
 
-  %result = zext i1 %test to i32
-  ret i32 %result
+  ret <4 x float> %x
 }