Add fabs(<4 x float>) to the integrated ARM assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 306 matching lines @@
             CondARM32::Cond Cond);
 
   void umull(const Operand *OpRdLo, const Operand *OpRdHi, const Operand *OpRn,
              const Operand *OpRm, CondARM32::Cond Cond);
 
   // Implements uxtb/uxth depending on type of OpSrc0.
   void uxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond);
 
   void vabss(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond);
 
-  void vabsd(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond);
+  void vabsd(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond Cond);
+
+  void vabsq(const Operand *OpQd, const Operand *OpQm);
 
   void vaddd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
              CondARM32::Cond Cond);
 
   void vadds(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
              CondARM32::Cond Cond);
 
   // Integer vector add.
   void vaddqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQm,
               const Operand *OpQn);
@@ skipping 234 matching lines @@
     DA_W = (0 | 0 | 1) << 21, // decrement after with writeback to base
     IA_W = (0 | 4 | 1) << 21, // increment after with writeback to base
     DB_W = (8 | 0 | 1) << 21, // decrement before with writeback to base
     IB_W = (8 | 4 | 1) << 21  // increment before with writeback to base
   };
 
   Label *getOrCreateLabel(SizeT Number, LabelVector &Labels);
 
   void bindCfgNodeLabel(const CfgNode *Node) override;
 
+  // SIMD encoding for the vector ElmtTy.
+  static IValueT encodeElmtType(Type ElmtTy);
+
   void emitInst(IValueT Value) {
     AssemblerBuffer::EnsureCapacity _(&Buffer);
     Buffer.emit<IValueT>(Value);
   }
 
   // List of possible checks to apply when calling emitType01() (below).
   enum EmitChecks { NoChecks, RdIsPcAndSetFlags };
 
   // Pattern cccctttoooosnnnnddddiiiiiiiiiiii where cccc=Cond, ttt=InstType,
   // s=SetFlags, oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM
@@ skipping 99 matching lines @@
                  const Operand *OpRm, const Operand *OpSrc1,
                  const bool SetFlags, const char *InstName);
 
   // Implements various forms of signed/unsigned extend value, using pattern
   // ccccxxxxxxxxnnnnddddrr000111mmmm where cccc=Cond, xxxxxxxx<<20=Opcode,
   // nnnn=Rn, dddd=Rd, rr=Rotation, and mmmm=Rm.
   void emitSignExtend(CondARM32::Cond, IValueT Opcode, const Operand *OpRd,
                       const Operand *OpSrc0, const char *InstName);
 
   // Implements various forms of vector (SIMD) operations.  Implements pattern
-  // 111100100Dssnnnndddn0000NQM0mmmm where ss=encodeElmtType(ElmtTy), Dddd=Dd,
-  // Nnnn=Dn, Mmmm=Dm, Q=UseQRegs, and Opcode is unioned into the pattern.
+  // 111100100D00nnnndddn00F0NQM0mmmm where Dddd=Dd, Nnnn=Dn, Mmmm=Dm,
+  // Q=UseQRegs, F=IsFloatTy, and Opcode is unioned into the pattern.
+  void emitSIMDBase(IValueT Opcode, IValueT Dd, IValueT Dn, IValueT Dm,
+                    bool UseQRegs, bool IsFloatTy);
+
+  // Same as emitSIMDBase above, except ElmtShift=20 and ElmtSize is computed
+  // from ElmtTy.
   void emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd, IValueT Dn, IValueT Dm,
                 bool UseQRegs);
 
   // Implements various integer forms of vector (SIMD) operations using Q
-  // registers. Implements pattern 111100100Dssnnn0ddd00000N1M0mmm0 where
-  // ss=encodeElmtType(ElmtTy), Dddd=Qd, Nnnn=Qn, Mmmm=Qm, and Opcode is unioned
-  // into the pattern.
+  // registers. Implements pattern 111100100D00nnn0ddd000F0N1M0mmm0 where
+  // Dddd=Qd, Nnnn=Qn, Mmmm=Qm, F=IsFloatTy, and Opcode is unioned into the
+  // pattern.
+  void emitSIMDqqqBase(IValueT Opcode, const Operand *OpQd, const Operand *OpQn,
+                       const Operand *OpQm, bool IsFloatTy,
+                       const char *OpcodeName);
+
+  // Same as emitSIMD above, except ElmtShift=20 and ElmtSize is computed from
+  // ElmtTy.
   void emitSIMDqqq(IValueT Opcode, Type ElmtTy, const Operand *OpQd,
                    const Operand *OpQn, const Operand *OpQm,
                    const char *OpcodeName);
 
   // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn,
   // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from
   // OpSrc1, and xxxx=Opcode.
   void emitCompareOp(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRn,
                      const Operand *OpSrc1, const char *CmpName);
 
@@ skipping 22 matching lines @@
 
   void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd,
                   const Operand *OpSn, const Operand *OpSm,
                   const char *InstName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H