Add fabs(<4 x float>) to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 126 matching lines @@
 }
 
 RegARM32::GPRRegister decodeGPRRegister(IValueT R) {
   return static_cast<RegARM32::GPRRegister>(R);
 }
 
 IValueT encodeCondition(CondARM32::Cond Cond) {
   return static_cast<IValueT>(Cond);
 }
 
-// Returns the SIMD encoding of the element type for the vector.
-IValueT encodeElmtType(Type ElmtTy) {
-  switch (ElmtTy) {
-  case IceType_i8:
-  case IceType_f32:
-    return 0;
-  case IceType_i16:
-    return 1;
-  case IceType_i32:
-    return 2;
-  case IceType_i64:
-    return 3;
-  default:
-    llvm::report_fatal_error("SIMD op: Don't understand element type " +
-                             typeIceString(ElmtTy));
-  }
-}
-
 IValueT encodeShift(OperandARM32::ShiftKind Shift) {
   // Follows encoding in ARM section A8.4.1 "Constant shifts".
   switch (Shift) {
   case OperandARM32::kNoShift:
   case OperandARM32::LSL:
     return 0; // 0b00
   case OperandARM32::LSR:
     return 1; // 0b01
   case OperandARM32::ASR:
     return 2; // 0b10
@@ skipping 437 matching lines @@
   const bool IsMovw = kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ||
                       kind() == llvm::ELF::R_ARM_MOVW_PREL_NC;
   Str << "\t"
          "mov" << (IsMovw ? "w" : "t") << "\t"
       << RegARM32::getRegName(RegNumT::fixme((Inst >> kRdShift) & 0xF))
       << ", #:" << (IsMovw ? "lower" : "upper") << "16:" << symbol(Ctx, &Asm)
       << "\t@ .word " << llvm::format_hex_no_prefix(Inst, 8) << "\n";
   return InstARM32::InstSize;
 }
 
+IValueT AssemblerARM32::encodeElmtType(Type ElmtTy) {
+  switch (ElmtTy) {
+  case IceType_i8:
+    return 0;
+  case IceType_i16:
+    return 1;
+  case IceType_i32:
+  case IceType_f32:
+    return 2;
+  case IceType_i64:
+    return 3;
+  default:
+    llvm::report_fatal_error("SIMD op: Don't understand element type " +
+                             typeIceString(ElmtTy));
+  }
+}
+
 // This fixup points to an ARM32 instruction with the following format:
 void MoveRelocatableFixup::emitOffset(Assembler *Asm) const {
   // cccc00110T00iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd,
   // iiiiiiiiiiiiiiii = Imm16, and T=1 for movt.
 
   const IValueT Inst = Asm->load<IValueT>(position());
   constexpr IValueT Imm16Mask = 0x000F0FFF;
   const IValueT Imm16 = offset() & 0xffff;
   Asm->store(position(),
              (Inst & ~Imm16Mask) | ((Imm16 >> 12) << 16) | (Imm16 & 0xfff));
@@ skipping 510 matching lines @@
   IValueT Rot = encodeRotation(Rotation);
   if (!Utils::IsUint(2, Rot))
     llvm::report_fatal_error(std::string(InstName) +
                              ": Illegal rotation value");
   IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | Opcode |
                      (Rn << kRnShift) | (Rd << kRdShift) |
                      (Rot << kRotationShift) | B6 | B5 | B4 | (Rm << kRmShift);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::emitSIMDBase(IValueT Opcode, IValueT Dd, IValueT Dn,
+                                  IValueT Dm, bool UseQRegs, bool IsFloatTy) {
+  const IValueT Encoding =
+      Opcode | B25 | (encodeCondition(CondARM32::kNone) << kConditionShift) |
+      (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
+      (getXXXXInRegYXXXX(Dd) << 12) | (IsFloatTy ? B10 : 0) |
+      (getYInRegYXXXX(Dn) << 7) | (encodeBool(UseQRegs) << 6) |
+      (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd,
                               IValueT Dn, IValueT Dm, bool UseQRegs) {
-  IValueT Sz = encodeElmtType(ElmtTy);
-  assert(Utils::IsUint(2, Sz));
-  IValueT Encoding =
-      Opcode | B25 | (encodeCondition(CondARM32::kNone) << kConditionShift) |
-      (Sz << 20) | (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
-      (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |
-      (encodeBool(UseQRegs) << 6) | (getYInRegYXXXX(Dm) << 5) |
-      getXXXXInRegYXXXX(Dm);
-  emitInst(Encoding);
+  constexpr IValueT ElmtShift = 20;
+  const IValueT ElmtSize = encodeElmtType(ElmtTy);
+  assert(Utils::IsUint(2, ElmtSize));
+  emitSIMDBase(Opcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs,
+               isFloatingType(ElmtTy));
+}
+
+void AssemblerARM32::emitSIMDqqqBase(IValueT Opcode, const Operand *OpQd,
+                                     const Operand *OpQn, const Operand *OpQm,
+                                     bool IsFloatTy, const char *OpcodeName) {
+  const IValueT Qd = encodeQRegister(OpQd, "Qd", OpcodeName);
+  const IValueT Qn = encodeQRegister(OpQn, "Qn", OpcodeName);
+  const IValueT Qm = encodeQRegister(OpQm, "Qm", OpcodeName);
+  constexpr bool UseQRegs = true;
+  emitSIMDBase(Opcode, mapQRegToDReg(Qd), mapQRegToDReg(Qn), mapQRegToDReg(Qm),
+               UseQRegs, IsFloatTy);
 }
 
 void AssemblerARM32::emitSIMDqqq(IValueT Opcode, Type ElmtTy,
                                  const Operand *OpQd, const Operand *OpQn,
                                  const Operand *OpQm, const char *OpcodeName) {
-  IValueT Qd = encodeQRegister(OpQd, "Qd", OpcodeName);
-  IValueT Qn = encodeQRegister(OpQn, "Qn", OpcodeName);
-  IValueT Qm = encodeQRegister(OpQm, "Qm", OpcodeName);
-  constexpr bool UseQRegs = true;
-  emitSIMD(Opcode, ElmtTy, mapQRegToDReg(Qd), mapQRegToDReg(Qn),
-           mapQRegToDReg(Qm), UseQRegs);
+  constexpr IValueT ElmtShift = 20;
+  const IValueT ElmtSize = encodeElmtType(ElmtTy);
+  assert(Utils::IsUint(2, ElmtSize));
+  emitSIMDqqqBase(Opcode | (ElmtSize << ElmtShift), OpQd, OpQn, OpQm,
+                  isFloatingType(ElmtTy), OpcodeName);
 }
 
 void AssemblerARM32::emitVFPddd(CondARM32::Cond Cond, IValueT Opcode,
                                 IValueT Dd, IValueT Dn, IValueT Dm) {
   assert(Dd < RegARM32::getNumDRegs());
   assert(Dn < RegARM32::getNumDRegs());
   assert(Dm < RegARM32::getNumDRegs());
   assert(CondARM32::isDefined(Cond));
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9 | B8;
   const IValueT Encoding =
@@ skipping 1058 matching lines @@
   emitVFPsss(Cond, VabssOpcode, Sd, S0, Sm);
 }
 
 void AssemblerARM32::vabsd(const Operand *OpDd, const Operand *OpDm,
                            CondARM32::Cond Cond) {
   // VABS - ARM section A8.8.280, encoding A2:
   //   vabs<c>.f64 <Dd>, <Dm>
   //
   // cccc11101D110000dddd101111M0mmmm where cccc=Cond, Ddddd=Dd, and Mmmmm=Dm.
   constexpr const char *Vabsd = "vabsd";
-  IValueT Dd = encodeDRegister(OpDd, "Dd", Vabsd);
-  IValueT Dm = encodeDRegister(OpDm, "Dm", Vabsd);
+  const IValueT Dd = encodeDRegister(OpDd, "Dd", Vabsd);
+  const IValueT Dm = encodeDRegister(OpDm, "Dm", Vabsd);
   constexpr IValueT D0 = 0;
   constexpr IValueT VabsdOpcode = B23 | B21 | B20 | B7 | B6;
   emitVFPddd(Cond, VabsdOpcode, Dd, D0, Dm);
 }
 
+void AssemblerARM32::vabsq(const Operand *OpQd, const Operand *OpQm) {
+  // VABS - ARM section A8.8.280, encoding A1:
+  //   vabs.<dt> <Qd>, <Qm>
+  //
+  // 111100111D11ss01ddd0f1101M0mmm0 where Dddd=OpQd, Mddd=OpQm, and
+  // <dt> in {s8, s16, s32, f32} and ss is the encoding of <dt>.
+  const Type ElmtTy = typeElementType(OpQd->getType());
+  assert(ElmtTy != IceType_i64 && "vabsq doesn't allow i64!");
+  constexpr const char *Vabsq = "vabsq";
+  const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vabsq));
+  const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vabsq));
+  constexpr IValueT Dn = 0;
+  const IValueT VabsqOpcode =
+      B24 | B23 | B21 | B20 | B16 | B9 | B8 | (encodeElmtType(ElmtTy) << 18);
+  constexpr bool UseQRegs = true;
+  emitSIMDBase(VabsqOpcode, Dd, Dn, Dm, UseQRegs, isFloatingType(ElmtTy));
+}
+
 void AssemblerARM32::vadds(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VADD (floating-point) - ARM section A8.8.283, encoding A2:
   //   vadd<c>.f32 <Sd>, <Sn>, <Sm>
   //
   // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
   constexpr const char *Vadds = "vadds";
   constexpr IValueT VaddsOpcode = B21 | B20;
   emitVFPsss(Cond, VaddsOpcode, OpSd, OpSn, OpSm, Vadds);
 }
 
 void AssemblerARM32::vaddqi(Type ElmtTy, const Operand *OpQd,
                             const Operand *OpQm, const Operand *OpQn) {
   // VADD (integer) - ARM section A8.8.282, encoding A1:
   //   vadd.<dt> <Qd>, <Qn>, <Qm>
   //
   // 111100100Dssnnn0ddd01000N1M0mmm0 where Dddd=OpQd, Nnnn=OpQm, Mmmm=OpQm,
   // and dt in [i8, i16, i32, i64] where ss is the index.
+  assert(isScalarIntegerType(ElmtTy) &&
+         "vaddqi expects vector with integer element type");
   constexpr const char *Vaddqi = "vaddqi";
   constexpr IValueT VaddqiOpcode = B11;
   emitSIMDqqq(VaddqiOpcode, ElmtTy, OpQd, OpQm, OpQn, Vaddqi);
 }
 
 void AssemblerARM32::vaddqf(const Operand *OpQd, const Operand *OpQn,
                             const Operand *OpQm) {
   // VADD (floating-point) - ARM section A8.8.283, Encoding A1:
   //   vadd.f32 <Qd>, <Qn>, <Qm>
   //
   // 111100100D00nnn0ddd01101N1M0mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
+  assert(OpQd->getType() == IceType_v4f32 && "vaddqf expects type <4 x float>");
   constexpr const char *Vaddqf = "vaddqf";
-  constexpr IValueT VaddqfOpcode = B11 | B10 | B8;
-  emitSIMDqqq(VaddqfOpcode, IceType_f32, OpQd, OpQn, OpQm, Vaddqf);
+  constexpr IValueT VaddqfOpcode = B11 | B8;
+  constexpr bool IsFloatTy = true;
+  emitSIMDqqqBase(VaddqfOpcode, OpQd, OpQn, OpQm, IsFloatTy, Vaddqf);
 }
 
 void AssemblerARM32::vaddd(const Operand *OpDd, const Operand *OpDn,
                            const Operand *OpDm, CondARM32::Cond Cond) {
   // VADD (floating-point) - ARM section A8.8.283, encoding A2:
   //   vadd<c>.f64 <Dd>, <Dn>, <Dm>
   //
   // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vaddd = "vaddd";
@@ skipping 251 matching lines @@
       B25 | B24 | B8 | B4 |
       (encodeCondition(CondARM32::Cond::kNone) << kConditionShift) |
       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
       (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |
       (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::veorq(const Operand *OpQd, const Operand *OpQn,
                            const Operand *OpQm) {
+  // VEOR - ARM section A8.8.316, encoding A1:
+  //   veor <Qd>, <Qn>, <Qm>
+  //
+  // 111100110D00nnn0ddd00001N1M1mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
   constexpr const char *Veorq = "veorq";
   constexpr IValueT VeorqOpcode = B24 | B8 | B4;
   emitSIMDqqq(VeorqOpcode, IceType_i8, OpQd, OpQn, OpQm, Veorq);
 }
 
 void AssemblerARM32::vldrd(const Operand *OpDd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VLDR - ARM section A8.8.333, encoding A1.
   //   vldr<c> <Dd>, [<Rn>{, #+/-<imm>}]
   //
@@ skipping 357 matching lines @@
   emitVFPddd(Cond, VmuldOpcode, OpDd, OpDn, OpDm, Vmuld);
 }
 
 void AssemblerARM32::vmulqi(Type ElmtTy, const Operand *OpQd,
                             const Operand *OpQn, const Operand *OpQm) {
   // VMUL, VMULL (integer and polynomial) - ARM section A8.8.350, encoding A1:
   //   vmul<c>.<dt> <Qd>, <Qn>, <Qm>
   //
   // 111100100Dssnnn0ddd01001NqM1mmm0 where Dddd=Qd, Nnnn=Qn, Mmmm=Qm, and
   // dt in [i8, i16, i32] where ss is the index.
+  assert(isScalarIntegerType(ElmtTy) &&
+         "vmulqi expects vector with integer element type");
   assert(ElmtTy != IceType_i64 && "vmulqi on i64 vector not allowed");
   constexpr const char *Vmulqi = "vmulqi";
   constexpr IValueT VmulqiOpcode = B11 | B8 | B4;
   emitSIMDqqq(VmulqiOpcode, ElmtTy, OpQd, OpQn, OpQm, Vmulqi);
 }
 
 void AssemblerARM32::vmulqf(const Operand *OpQd, const Operand *OpQn,
                             const Operand *OpQm) {
   // VMUL (floating-point) - ARM section A8.8.351, encoding A1:
   //   vmul.f32 <Qd>, <Qn>, <Qm>
   //
   // 111100110D00nnn0ddd01101MqM1mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
+  assert(OpQd->getType() == IceType_v4f32 && "vmulqf expects type <4 x float>");
   constexpr const char *Vmulqf = "vmulqf";
-  constexpr IValueT VmulqfOpcode = B24 | B11 | B10 | B8 | B4;
-  emitSIMDqqq(VmulqfOpcode, IceType_f32, OpQd, OpQn, OpQm, Vmulqf);
+  constexpr IValueT VmulqfOpcode = B24 | B11 | B8 | B4;
+  constexpr bool IsFloatTy = true;
+  emitSIMDqqqBase(VmulqfOpcode, OpQd, OpQn, OpQm, IsFloatTy, Vmulqf);
 }
 
 void AssemblerARM32::vorrq(const Operand *OpQd, const Operand *OpQm,
                            const Operand *OpQn) {
   // VORR (register) - ARM section A8.8.360, encoding A1:
   //   vorr <Qd>, <Qn>, <Qm>
   //
   // 111100100D10nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm.
   constexpr const char *Vorrq = "vorrq";
   constexpr IValueT VorrqOpcode = B21 | B8 | B4;
@@ skipping 90 matching lines @@
   emitVFPddd(Cond, VsubdOpcode, OpDd, OpDn, OpDm, Vsubd);
 }
 
 void AssemblerARM32::vsubqi(Type ElmtTy, const Operand *OpQd,
                             const Operand *OpQm, const Operand *OpQn) {
   // VSUB (integer) - ARM section A8.8.414, encoding A1:
   //   vsub.<dt> <Qd>, <Qn>, <Qm>
   //
   // 111100110Dssnnn0ddd01000N1M0mmm0 where Dddd=OpQd, Nnnn=OpQm, Mmmm=OpQm,
   // and dt in [i8, i16, i32, i64] where ss is the index.
+  assert(isScalarIntegerType(ElmtTy) &&
+         "vsubqi expects vector with integer element type");
   constexpr const char *Vsubqi = "vsubqi";
   constexpr IValueT VsubqiOpcode = B24 | B11;
   emitSIMDqqq(VsubqiOpcode, ElmtTy, OpQd, OpQm, OpQn, Vsubqi);
 }
 
 void AssemblerARM32::vsubqf(const Operand *OpQd, const Operand *OpQn,
                             const Operand *OpQm) {
   // VSUB (floating-point) - ARM section A8.8.415, Encoding A1:
   //   vsub.f32 <Qd>, <Qn>, <Qm>
   //
   // 111100100D10nnn0ddd01101N1M0mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
+  assert(OpQd->getType() == IceType_v4f32 && "vsubqf expects type <4 x float>");
   constexpr const char *Vsubqf = "vsubqf";
-  constexpr IValueT VsubqfOpcode = B21 | B11 | B10 | B8;
+  constexpr IValueT VsubqfOpcode = B21 | B11 | B8;
   emitSIMDqqq(VsubqfOpcode, IceType_f32, OpQd, OpQn, OpQm, Vsubqf);
 }
 
 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
                                   const Variable *OpBaseReg,
                                   SizeT NumConsecRegs) {
   const IValueT BaseReg = getEncodedSRegNum(OpBaseReg);
   const IValueT DLastBit = mask(BaseReg, 0, 1); // Last bit of base register.
   const IValueT Rd = mask(BaseReg, 1, 4);       // Top 4 bits of base register.
   assert(0 < NumConsecRegs);
@@ skipping 59 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice